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User9635
Level 4
Level 4
50 replies posted 50 questions asked 25 replies posted
Hello Support,

In the Aurix TC3xx User Manual 1.4 version,

"Separate ACCEN protection range for Safety Watchdog Timer" in Section 9.4.1.1 is mentioned.
Can you please provide me the corresponding details about which Registers this above line is referring so that I can understand better how Safety WDT can be accessed by a particular CPU in default state of ACCENxx register?
I am assuming by default any CPU can write to Safety WDT similar to Aurix TC2xx devices.
Thank you.
Regards
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3 Replies
VincentWan
Employee
Employee
First like received 25 replies posted 10 replies posted
Hi

Yes, any CPUx can access safety-endinit protected registers.
Users need to disable safety-endinit before writing to those register, same procedures as endinit protected registers.

The following registers are ENDINIT protected:
• BTV, BIV, ISP, PMA0, PMA1, PMA2, PCON0, DCON0, SEGEN

A safety specific version of ENDINIT protection is provided. The following registers are SAFETY_ENDINIT
protected:
• SMACON, SYSCON, COMPAT, TPS_EXTIM_ENTRY_LVAL, TPS_EXTIM_EXIT_LVAL

ACCEN is referring to The Access Enable (ACCEN) Register which restricts write access so that they
may only be written by specified bus masters (eg CPUs). By default after reset, no restriction of write access for all masters.
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User9635
Level 4
Level 4
50 replies posted 50 questions asked 25 replies posted
Hello Vincent,

The original statement I attached is in a section within the TC3xx User Manual, which says that it is different from TC2xx features.
But as far as I can tell, TC2xx also had the same ACCEN based Protection feature for WDT registers and also by default any bus masters could write to Safety WDT registers because ACCEN contents were 0xFFFF_FFFF.
Same thing I see for TC3xx Manual.
So, the question is why that statement in that section within TC3xx?
Hope my question is clear.
Thank you.
Regards
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NeMa_4793301
Level 6
Level 6
10 likes received 10 solutions authored 5 solutions authored
Hi baexps_pr1. In the TC2xx, there was only one set of access enable registers for the SCU: SCU_ACCEN0 and SCU_ACCEN1.

In the TC3xx, access was split into SCU_ACCEN00/01 and SCU_ACCEN10/11. SCU_ACCEN10 and SCU_ACCEN11 control which bus masters can manipulate the Safety Watchdog. See pages 672 and 673 in AURIXTC3XX_um_part1_v1.3.pdf:

Access Enable Register 10
The Access Enable Register 1 restricts write access to SCU, RCU, CCU and PMC registers marked “P1” so that they may only be written by specified bus masters (eg CPUs). See the Bus chapter for the mapping of TAG ID to specific system masters and CPUs).


The affected registers are listed as "P1" entries on page 731: WDTSCON0, WDTSCON1, SEICON0, and SEIICON1.
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