Safety Flip-Flops in CCU - AURIX TC3xx

[nsyed]

Section 10.2.1 of the AURIX TC3xx User’s Manual indicates that CCU has safety Flip-Flops implemented to detect Single Event Upsets. Can you please provide more information about this feature.

Our application has run-time register check implemented. Safety Critical Clock registers are initialized at Power-Up and read back/compared every FTTI window. In the event of failure system goes to the safe state as clock registers are compromised. We followed this approach to detect any Single Event Upsets in the safety critical registers.

What are the features of the Safety Flip-Flops in AURTIX TC3xx. Can we configure the CCU to generate any reaction to SMU in the event of SEU ?
Does the clock registers have built-In safety protection against bit flips due to SEU ?

[NeMa_4793301]

The Safety Flip-Flops are simply a redundant set of bits that mirror each of the specified registers. If the SMU detects a discrepancy between a register and its copy, it triggers an SMU alarm.

You can configure the reaction for all of the Safety Flip-flop alarms: ALM6[0] for MTU, ALM6[4] for SCU, etc.

The registers listed in each "Safety Flip-Flops" section of the User Manual are covered.

[nsyed]

Thank you so much. Appreciate your feedback !!!