STMEM Registers

[Mmmmmm]

Value of STMEM3 as example after Cold power on reset is A0F3FB1F in user manual but while debugging it's value 0x80f3ff1f 

problem in bit 10 which must be reserved 1 , and bit 29 which indicate Flashcon1 register check is started 

how i solve problem of reserved bit and how start Flashcon1 register check ?

[DownyK]

How did you set the BMI? 

[Mmmmmm]

yes it's enabled, all another's checks are started and passed successfully only the Flashcon1 register and bit10 which is reserved bit 

[DownyK]

how are you checking SCU_STMEM3? 

did you use Trace 32 with PER file? or memory dump?

[Mmmmmm]

Memory dump , that values after warm reset and also the same problem 

[DownyK]

um... this is so strange. 

how can the bit 10 be high?

I don't understand.

You checked the BMI, too, didn't you?

Did you check other parts besides the CHSW area?

Then there won't be anything wrong...

In my case, there was a problem with other registers during the FW check stage, but there was no STMEM.

That memory dump address is correct. Right?

I think you should contact an Infenion employee.

[Mmmmmm]

What problems did you encounter ?

[DownyK]

My problem was more of a problem with the Reset Reason being erased after Cold Power Reset than a Register problem. It is Cold Power On Reset, but the MCU recognized it as a different Reset and determined that the Register value was not correct.

In addition, there was a time when System Reset occurred by turning on SMU CLC and performing FW Check, so I changed SMU reset to No reset.

Other than these issues, there has never been an issue like what you said...

[Nambi · Accepted solution]

The question is resolved at the thread https://community.infineon.com/t5/AURIX/SCU-registers/m-p/403054