Announcements

Equip yourself to optimize AURIX™ MCUs for Evs at the EV Webinar. Click here to register.

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

AURIX™ Forum Discussions

User21319
Level 1
Level 1
Using the GPSR source to handle the inter core communication, and while setting the SETR from core0 to notify core1 that there is new data in the queue, the SRE bit is cleared "disabled".
This doesn't happen from the begining, it works for some time, like after 10 notifications from core0 to core1, this issue happens.
Because the SRE bit is cleared, core0 remains filling the queue and notifying core1 with no response from core1, and so the queue is full, the used AUTOSAR OS is then stuck waiting for the queue to be freed.
This is detected by making hardware breakpoint on any write to the register, it comes like 9 times normal, because of setting SRR, then when the 10th comes, the SRR is set but also the SRE is cleared.
The other inter core communication are working fine, between core0 and core2, both of them are communicating and the SRE bit remains enabled.
Also after this issue happens, when I enable the SRE bit for core1 manually in the debugger, it works fine afterwards and the issue doesn't happen again.
Any ideas or thoughts regarding this?
0 Likes
1 Reply
NeMa_4793301
Level 6
Level 6
10 likes received 10 solutions authored 5 solutions authored
I get the idea, but can you describe what values you're writing to which registers?
0 Likes