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I use SPI+DMA for data transmission and transmission, and I need to write two interrupt service functions, but after searching for a long time, I didn't find out under what conditions these two interrupt service functions were triggered, and whether any bosses who have done it have transmission experience, kneeled down and asked

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/SPI-DMA/td-p/659630

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Hello,

There are two ways to configure SPI here. Do you want to use QSPI or the SPI mode in ASCLIN? Are you saying that writing two interrupt service functions means when sending and receiving SPI? 1.1/1.2 is the ASCLIN method, 2 is the QSPI method.

 

1.1) This can be used as a reference for ASCLIN to set SPI mode to trigger DMA:

asclin_spi_master_1_kit_tc375_lk

Service selection dma: spimasterConfig. Interrupt. TypeOfService = ifxsrc_tos_dma; //in the example code is ifxsrc_tos_cp0
 
1.2) This is a reference on how to configure dma:
 
2) This reference shows how to use the QSPI module to configure SPI and DMA
Related reference functions such as: initQSPI2master, ifxQSPI_spimaster_initModuleConfig, ifxQSPI_spimaster_initchannel
 
DMA triggers are generated when writing TXFIFO and reading RXFIFO. For details on the mode of interruption, please refer to um 37.3.6
 
 
 

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/SPI-DMA/m-p/659786

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Yes, service functions for receiving and sending

I'm using QSPI+DMA, but I can't figure out when to stop the service function. Just these two functions in the following figure

_0-1702602073807.png

 

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/SPI-DMA/m-p/660235

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Hello,

Are you saying he doesn't stop responding, or every time he goes in, you don't know when? This should be a CPU0 interrupt that is triggered every time a DMA transaction is completed.

Kunqiao_L_0-1702608083945.png

 

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/SPI-DMA/m-p/660342

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Right, I don't know when it went in; I wanted to know when it went in. It is reasonable to say that you can only enter after a change in the position of the sign, but I haven't been able to find this sign

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/SPI-DMA/m-p/660347

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Hello, your sample code is configured to interrupt CPU0 when the DMA transaction is complete.

In the interrupted state, it is register ICR.

For DMA, please refer to User Manual 18.4 to see these registers first: CHCSRC (DMARAM Channel C Control and Status Register), TSRC (DMA Channel C Transaction State Register)

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/SPI-DMA/m-p/660371

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I looked for it, but I didn't find any changes

I used a new method for transmission, that is, I don't turn on the CPU0 interrupt, but just open the DMA channel. Then, let's stop the service function and run it below, it's OK

_0-1702617083355.jpeg_1-1702617096056.jpeg

 

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/SPI-DMA/m-p/660477

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You can do this too, that is, every DMA transaction (the configuration should be just a transfer, one move, one byte DMA,) will not trigger an interruption after the DMA is completed, so there is no need for ISR

ifxQSPI_spimaster_isrdmaTransmit. Use while to get him to turn on the next send.
 
 

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/SPI-DMA/m-p/660504

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Interruptions have the same transmission effect as my method. When debugging, you'll find out, for example, if 16 8-bit numbers are transmitted, 15 are transmitted first, then the interrupt function type is transmitted, and then the last one is transmitted

In my mode of not starting and interrupting, I also transfer 15 first, then while for the last data transmission

Question: Why is that? I read the chip manual and didn't understand it, but this setting is indeed correct in terms of transmission effect

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/SPI-DMA/m-p/660522

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I'll try the sample code later. What's the difference between the code you're debugging and the example code, except for the fact that you've changed not to open interrupts and the buffersize has changed from 8 to 16

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/SPI-DMA/m-p/660533

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I used the 275D sample code for debugging. Other than changing the part of my screenshot, nothing else has changed

 

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/SPI-DMA/m-p/660534

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Hello, he should have adjusted the transfer count according to SPI_BUFFER_SIZE during SPIMASTER_WRITE and SPISLAVE_WRITE. As a result, the above effects have occurred

Kunqiao_L_0-1702638525294.png

Kunqiao_L_1-1702638552367.png

 

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/SPI-DMA/m-p/660882

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Hello, what is the meaning of this job- > motivation - 1? I don't understand at all

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/SPI-DMA/m-p/661135

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I just debugged and looked at it. It is true that his transmission mechanism is to receive all of the data when it occurs minus one data,

So the question is, why is the data being reduced by one? Is it because the last transmission triggers an interruption?

 

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/SPI-DMA/m-p/661139

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I don't know about this question either. I tried it without using “-1” and there was no problem; it probably has something to do with whether the SPI frame is the last one (BACON.LAST). I'll go talk to the code owner and give you feedback if there are any results

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/SPI-DMA/m-p/661935

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Right, I don't know when it went in; I wanted to know when it went in. It is reasonable to say that you can only enter after a change in the position of the sign, but I haven't been able to find this sign

 

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/SPI-DMA/m-p/660346

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