SPI DMA Master - Slave Data Exchange of length more than 16bytes

[User22868]

Good Morning,

I am working on TC3x4T board for my project in which I would like to use two QSPI modules. One as MASTER and the other as SLAVE.  My goal is to have a periodic (e.g.: every 10ms) data exchange between Master and Slave of data length of 64bytes. And I would like to use DMA for this data exchange to minimize the cpu intervention. And I would like to trigger DMA via software (i.e. For example..I do not want to use Hardware trigger via Timer interrupt). 

I am new to both QSPI and DMA. I know QSPI FIFO has 4 x 32-bit buffers which would be 16bytes.

So, as a first step, using just one QSPI module as MASTER in Loop back mode,  I tried below combination to transmit 16bytes of data and check my Rx buffer (in RAM) is receiving the data that MASTER transmit. And it seems to be working or atleast I can see the data transmitted is being updated to RAM Buffer via loop back mode.

Here is what I did

1) Initialize one of my QPSI module as MASTER in Loop Back Mode with Transmission mode set to Short (DL = 31, BYTE = 0, LAST = 1)

2) Initialize DMA Channel #1 for MASTER Transmission with Source Address set to RAM buffer, Destination Address set to QSPI_DATAENTRY0 and by using Single transaction with 4 Transfers (each Transfer with one 32-bit move)

3) Initialize DMA Channel #2 for MASTER Reception with Source Address set to QSPI_DATAEXIT, Destination Address set to RAM buffer and by using Single transaction with 4 Transfers (each Transfer with one 32-bit move)

4) Enable the DMA channels for Tx and Rx in my periodic runnable based on TX/RX FIFO status.

I am attaching my code here (SPI_COM.c).

I have couple of questions regarding my project.

1) Is my understanding and implementation for 16bytes (4 x 32-bit) data exchange correct for my use case?

2) Would you please give any suggestions on how to modify this strategy so that I can exchange 64bytes of data ?

I am trying to understand the concept by analyzing the iLLD example code (SPI_DMA_1_KIT_TC397_TFT).. but it seems complicated and taking time and I am in a bit of urgency.

So, any help is much appreciated...

Thank you

[cwunder · Accepted solution]

You have many choices on how to configure the QSPI to achieve what you desire. 

1) Is my understanding and implementation for 16bytes (4 x 32-bit) data exchange correct for my use case?

Given that you want to transfer 64 byes of data you can transfer the data between the QSPI as 16 x 32 bit transfers. Then you would set up the DMA to TREL=16 and allow the QSPI interrupts to pull the data as the FIFO's require.

2) Would you please give any suggestions on how to modify this strategy so that I can exchange 64bytes of data ?

Here is some nuance needed depending on how you want the QSPI to behave since you cannot completely load all of your data at one time as this would exceed the FIFO size of the QSPI. One option for the QSPI is to operate it in "short mode continuous data".  However this also depends on how you want the bytes to be seen on the SPI bus. As the TriCore is a little endian machine and when transferring the bytes it depends on how you store them in memory. Below is a link to an example project  that can transfer the 64-bytes (as bytes, half-words or words to/from the QSPI) using DMA. The QSPI and DMA are configured using bare metal code (i.e. not using the iLLD's).

AURIX-TC364T-TriBoard-example-project-QSPI1-data-exchange-using-DMA-bare-metal 

[User22868]

@cwunder  Thank you for your kind reply. I have added comments related to example project in the provided link here (https://community.infineon.com/t5/Code-Examples/AURIX-TC364T-TriBoard-example-project-QSPI1-data-exc...). Would you kindly provide feedback? Thank you!