AURIX™ Forum Discussions

[DownyK]

Hello everyone.

I am curious about SMU core and SMU standby.

I think these two components are mutual monitoring parts.

when I run the SMU core, SMU standby also runs to monitor SMU Core or Embedded Voltages condition in PMS. 

is it right?

and SMU standby always runs without any control by the user, is it right?

thanks. 

[dw]

In chapter 15.3.3 Interdependency Between SMU_core and SMU_stdby in user manual, there is descrption for both two functions. The SMU_stdby can monitor SMU_core and notify an external device of a fault in the SMU_core.

For FSP generated by SMU_core, if SMU_core is not enabled, then SMU_stdby's reaction  to alarm cannot be noticeable.

[LaneYE]

Hi,

I add some comments from my side.

a. SMU_Standby located in standby domain, SMU_Core located in core domain.This two domain has physical isolation which includes power and clock.

b.as you know, PMS supports standby domain and core domain,  if the system isn't in standby mode, the SMU_core and SMU_Standby will active, the SMU_Standby should be disabled before goto system standby mode

c. Due to the SMU_Standby monitors voltage on chip, temperature ,access protection monitoring and SMU_Core aliving, the voltage, temperature and access protection monitoring could be a single point failure, so you should enable them, as for SMU_Core aliving monitoring, this is a dual point failure(because this is SM's monitoring) which can monitor the fault of SMU_Core and can decrease the FIT of latent fault, due to the physical isolation of SMU_Core and SMU_Standby, so the common failure of power and clock  could be avoided, additional, the power monitoring and temperature monitoring are achieved by both

d.For FSP, SMU_Standby could control ENPS, FSP0EN and FSP1IEN, so even the FSP is controlled by SMU_Core, bu the FSP port could be controlled by SMU_Standby

e.You should configure trigger SMU_core to run state, for SMU_Core, there has a state machine, you can reference SMU_core state machine; for SMU_Standby, you should enable the SMUEN bit in CMD_STDBY register

[DownyK]

Thanks, LaneYE

and I have another question about the relationship between PMS and SMU.

if I enable SMU_core and SMU_Standby also config SMU_Core 9[3] and 9[5] reaction to System_Reset, SMU_Standby 20[7] and 20[13] reaction to FSP, what reaction would be triggered in a situation that VDDM voltage is higher than OV threshold or VDDM voltage is lower than UV threshold.

[LaneYE]

Hi, DownyK 1. PMS and SMU are sub-Ips in AURIX -PMS: Power management system -SMU: Safety management unit, due to there are a lot of HW random failure, so the AURIX support HW mechanisms to detect HW failure, the SM-Ips will report error to SMU, and SMU can reaction according to fault action configure, such trigger FSP, NMI and so on. 2. Both, as I said, the power monitoring and temperature monitoring are detected by both, so the SMU_Core’s voltage monitoring is same with SMU_Standby. All voltage fault are collected in SMU_Core 9[3] and 9[5], and the detailed voltage faults are separated in ALM20[4]~ALM20[15], ALM21[0]… and so on(more information pls reference safety manual)

[LaneYE]

Hi, dw

Could you please specify the power rail supply for SMU_Standby and SMU_Core? I didn't find out the power rail for this two modules. In user manual, just said these two modules use different power rail, one in standby domain and other in core domain.