Level 4
Hello Support,
Related to SMU_TC.012 Errata in Aurix 1G TC29x device,
At cold power on reset SMU_FSP is in Bi-Stable state.
Then we enable Time-Switch Protocol using SMU_FSP by writing 0x00400050.
If we continuously write 0x00400050 after that with some delay of 100msec to SMU_FSP Register, do we expect to see this metastability related SMU_TC.012 Errata effect of sporadic ALM3[27]?
I am assuming yes, because even though Peripheral write may be buffered, but it is always a committed write cycle to the peripheral over SPB bus.
Please confirm soon, whether we expect to see ALM3[27].
Best Regards
Related to SMU_TC.012 Errata in Aurix 1G TC29x device,
At cold power on reset SMU_FSP is in Bi-Stable state.
Then we enable Time-Switch Protocol using SMU_FSP by writing 0x00400050.
If we continuously write 0x00400050 after that with some delay of 100msec to SMU_FSP Register, do we expect to see this metastability related SMU_TC.012 Errata effect of sporadic ALM3[27]?
I am assuming yes, because even though Peripheral write may be buffered, but it is always a committed write cycle to the peripheral over SPB bus.
Please confirm soon, whether we expect to see ALM3[27].
Best Regards
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