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AURIX™ Forum Discussions

User9635
Level 4
Level 4
50 replies posted 50 questions asked 25 replies posted
Hello Support,

In the attached snippet from Aurix 2G User Manual, there is a mention of Fevr_clk signal for RTAC.
I am unable to find that Fevr_clk in the "Table 281 CCU Clock Options"
Can you please help me with some documentation snippet where I can better understand Fevr_clk signal generation mechanism?
4286.attach
Best regards
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3 Replies
Darren_Galpin
Employee
Employee
First solution authored First like received
This is the EVR Clock - the EVR is described in the Power Management System chapter, Chapter 13.2.2.
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User9635
Level 4
Level 4
50 replies posted 50 questions asked 25 replies posted
Hello Support,
Shown below is a snippet with 100MHz block as well as /4 block in cascade.
So for the SMU_RTAC counter, which one is the input?
100MHz or 25MHz?
Please confirm.
4290.attach
Best Regards
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MoD
Employee
Employee
25 likes received 50 solutions authored 100 sign-ins
Have a look at UM V1.5 part 1 Figure 91. Here you can see that the SMU has two clock inputs: fsbp and fback which comes from EVR and is 100MHz (fixed).
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