May 13, 2020
09:40 AM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
May 13, 2020
09:40 AM
Hello Support,
In the attached snippet from Aurix 2G User Manual, there is a mention of Fevr_clk signal for RTAC.
I am unable to find that Fevr_clk in the "Table 281 CCU Clock Options"
Can you please help me with some documentation snippet where I can better understand Fevr_clk signal generation mechanism?
Best regards
In the attached snippet from Aurix 2G User Manual, there is a mention of Fevr_clk signal for RTAC.
I am unable to find that Fevr_clk in the "Table 281 CCU Clock Options"
Can you please help me with some documentation snippet where I can better understand Fevr_clk signal generation mechanism?
Best regards
- Tags:
- IFX
3 Replies
May 14, 2020
12:11 AM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
May 14, 2020
12:11 AM
This is the EVR Clock - the EVR is described in the Power Management System chapter, Chapter 13.2.2.
May 14, 2020
04:35 AM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
May 14, 2020
04:35 AM
Hello Support,
Shown below is a snippet with 100MHz block as well as /4 block in cascade.
So for the SMU_RTAC counter, which one is the input?
100MHz or 25MHz?
Please confirm.
Best Regards
Shown below is a snippet with 100MHz block as well as /4 block in cascade.
So for the SMU_RTAC counter, which one is the input?
100MHz or 25MHz?
Please confirm.
Best Regards
May 14, 2020
06:45 AM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
May 14, 2020
06:45 AM
Have a look at UM V1.5 part 1 Figure 91. Here you can see that the SMU has two clock inputs: fsbp and fback which comes from EVR and is 100MHz (fixed).