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cross mob
Level 1
Level 1
Some alarms are configured to trigger SMU1 interrupt.
But this interrupt is raised only once. It seams this is caused by the fact that bit IRQ1STS in the AEX register need to be reset.
To reset this bit I need to write the IRQ1CLR bit in AEXCLR register.
But this register is write protected, so I need to remove the END INIT protection.

But whatever I tried I did not managed to clear AEX.IRQ1STS.
I removed the Safety End Init, I tried also by removing the CPU end init.
I tried the MCAL function Smu_ClearAlarmExecutionStatus(), but with no success.

Can you please support me?
1 Reply
Level 6
Level 6
10 likes received 10 solutions authored 5 solutions authored
Hi dannydc89. AEXCLR is *safety* endinit protected, as specified in Table 539: the "SE" means Safety Endinit.

It could be that you cleared the SMU's IRQ1 flag, but the fault from the underlying hardware mechanism also needs to be cleared.

Which alarm are you getting?