SFR Registers are updated on RET & RFE instruction for AURIX 2G?

[User9635]

Hello Support,
In the TC1.6,2 Manual, I found the following sentence :
Figure 19 CSA and Processor SFR Updates on a Context Restore Process

Does the above sentence means all the SFR Registers as mentioned in the Table 109 of Part 1 Aurix 2G User Manual will be updated only on RET and RFE instruction execution, even though CPU writes to these registers?
Please elaborate more about the process of updated SFR Registers of Table 109, especially Bus MPU Protection Registers and ACCEN registers from that table.
What really means from the sentence about SFR update for "Figure 19 CSA and Processor SFR Updates on a Context Restore Process".
Relevant snippets are attached



Best Regards

[NeMa_4793301]

No, it doesn't include all SFRs. TriCore Architecture vol 1. Section 4.7 is only discussing what happens to the CSAs, FCX, and PCX. Only the registers in an upper context (see Figure 12) are restored by a RET/RFE.