SCU STCON register access mode

[MalolanSrinivas]

I would like to understand the following : 

The register STCON has access mode as ST, P0. P0 means a master can access it when accen bit is enabled.

1. I have opened the Trace32 and requested a Cold PORST. The execution in Trace32 is now at the start of the bootloader.

2. In this condition, I try to write 0 to this STP bit. But I get SPB bus error meaning the master(CERBERUS) cannot access it. The access enable bit for the master (here CERBERUS) is Enabled in SCU_ACCEN00/10. 

If only SSW can write this bit, Why is then the access mode P0 given ? Is it possible to modify the value to 0 at any point ?

[µC_Wrangler · Accepted solution]

ST means only the SSW can write to this register.  The debugger interface is only enabled after the ST state ends.

Technically, writing is also governed by the access protection mechanism - but that's irrelevant to your application, because you can't write to it anyway.  It would have been nicer if we had simply not included it in the User Manual.