SCU_STCON Register STP Bit for Aurix 2G

[User9635]

Hello Support,

In the AURIX 2G, there is a register SCU_STCON -- Start-up Configuration Register -- Offset 0xC4.
Bit 15 is STP.

Following sentences are in the User Manual Part 1 Revision 1.4 for STP bit

"
This bit will be always set by FW and can't be reset.
This bit is also cleared by an Application Reset.
STP is automatically set when a shutdown trap occurs.
"
1>
Looks like STP is cleared when Application Reset but during Cold Power On Reset it will be SET.
Is that correct?

2>
FW -- means Boot_ROM Firmware which is SSW
Is that correct?

3>
Can you please point me to documentation regarding "shutdown trap" as mentioned above?

Best Regards

[MoD]

1> STP will be cleared on Application Reset therefore also on Cold Power On Reset (Application Reset is a "part" Cold Power On Reset)
2> Yes, FW means the SSW
3> Please see chapter 9.1.3.2 Shutdown and Reset Delay Timeout Counter (TOUTCNT) in the UM V1.4 part 1

[MalolanSrinivas]

I totally understand the description for the bit. 

But the register STCON has access mode as ST, P0. P0 means a master can access it .

When I try to write 0 to this bit , I get SPB bus error meaning the master cannot access it. The access enable bit for the master is Enabled.  Why is then the access mode P0 given ? Is it possible to modify the value to 0 at any point ?

[µC_Wrangler]

Answered elsewhere - please just post questions in one spot 🙂