SBE Trap in TC275

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Jayanth
Level 1
Level 1
5 questions asked 10 sign-ins First reply posted

Hello All, 

I am using TC275 Lite Kit. I am getting SBE (Store Bus Error) / DAE Trap in the below highlighted line.

Attached the images of the Trap window and supporting documents.

#include "Ifx_Types.h"
#include "IfxCpu.h"
#include "IfxScuWdt.h"
#include "IfxQspi_reg.h"
#include "IfxQspi_bf.h"
#include "IfxStm_reg.h"

void Spi_Init(void)
{
/* initialize PORT pins for QSPI0 */
/* initialize I/O function */
P22_IOCR0.B.PC2 = 0x13; /* SLSO P20.13 */
P22_IOCR0.B.PC3 = 0x13; /* SCLK P20.11 */
P22_IOCR0.B.PC0 = 0x13; /* MTSR P20.14 */
P22_IOCR0.B.PC1 = 0x02; /* MRTS P20.12 */

/* Initialize speed grade */
P22_PDR0.B.PD2 = 0x02; /* medium */
P22_PDR0.B.PD3 = 0x01; /* strong, medium edge */
P22_PDR0.B.PD0 = 0x01; /* strong, medium edge */
P22_PDR0.B.PD1 = 0x00; /* default speed grade */

/* Initialize output */
P22_OUT.B.P2 = 0x01;
P22_OUT.B.P3 = 0x01;
P22_OUT.B.P0 = 0x01;
P22_OUT.B.P1 = 0x00;

/* enable QSPI device */
QSPI0_CLC.U = (unsigned long int)0x00000000;

/* set input line selection for MRST pin (PISEL.MRIS) */
QSPI0_PISEL.U = (unsigned long int) 0;

/* Enable Chip Select */
QSPI0_SSOC.U = 0x00040000;

/* set timing characteristics/profile for channel */
QSPI0_ECON2.U = 0x00000844;

/* set up spi device hardware */
QSPI0_GLOBALCON.U = 0x21000000;
QSPI0_GLOBALCON1.U = 0x11050400;

// clear any error flags that might get set during init process
QSPI0_FLAGSCLEAR.U = 0x1ffu;
}


int core0_main(void)
{

uint16 password = IfxScuWdt_getCpuWatchdogPassword();
IfxScuWdt_clearCpuEndinit(password);
Spi_Init();
IfxScuWdt_setCpuEndinit(password);
while(1)
{
}
return (1);
}

 

 

Trap Structure :

Jayanth_2-1687496374508.png

Trap Table to identify the trap:

Jayanth_3-1687496386599.png

DATR register : SBE bit is high.

Jayanth_1-1687496349560.png

 

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3 Replies
MoD
Employee
Employee
50 likes received 500 replies posted 100 solutions authored

Which address contains the register DEADD?

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Jayanth
Level 1
Level 1
5 questions asked 10 sign-ins First reply posted

I have attached a snapshot of DEADD register.

Jayanth_2-1687770433927.pngJayanth_3-1687770456048.png

 

 

 

 

 

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MoD
Employee
Employee
50 likes received 500 replies posted 100 solutions authored

The error address is P22_PDR0, this means the write don't work. I guess that the endinit bit is not cleared, I see the clear endinit but maybe there is a problem. Set a breakpoint to the first P22_PDR0 instruction, check at this place which state the CPUx endinit has and step trough the code.

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