Jun 15, 2020
03:20 AM
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Jun 15, 2020
03:20 AM
Hello,
What are the Root causes of SMU3[6] alarm in Aurix TC265D?
The clock configurations are proper according to the Errata sheet (5 MHz is selected as target monitoring frequency).
There are no other additional alarms are triggered and this SMU alarm is raised sporadically.
What are the Root causes of SMU3[6] alarm in Aurix TC265D?
The clock configurations are proper according to the Errata sheet (5 MHz is selected as target monitoring frequency).
There are no other additional alarms are triggered and this SMU alarm is raised sporadically.
- Tags:
- IFX
7 Replies
Jun 16, 2020
12:32 AM
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Jun 16, 2020
12:32 AM
Alarm3[6] is related to SRI(Shared Resource Interconnect) clock out of range frequency.
fSRI defines the operating performance of the SRI-Bus and therefore the data exchange rate between all connected masters and slaves
For example,
if the SPB is configured to operate at 100 MHz and needs to be monitored, CCUCON3.SBPDIV should be written with 0x14 and CCUCON3.SBPSEL with 00B.
This selects a target monitoring frequency of 5 MHz and divides the SPB clock by 20 resulting also in 5 MHz.
If the SPB is configured to operate at 20 MHz and needs to be monitored, CCUCON3.SBPDIV should be written with 0x04 and CCUCON3.SBPSEL with 00B.
If you configure 5MHz for target monitoring frequency, MCU operate to detect SRI clock error as below.
1) -12.41% > or 12.11% < , error is always detected
2) -12.41% ~ -3.9%, error can be detected. It means that error can’t be detected also
3) 2.83% ~ 12.11%, error can be detected. It means that error can’t be detected also
As I checked it, there is no mentioned about above range in TC26x user manual. only available LOWER and UPPER value
The range can be checked from "table 8-4 Target trimmed Check limits" in TC23x user manual.
fSRI defines the operating performance of the SRI-Bus and therefore the data exchange rate between all connected masters and slaves
For example,
if the SPB is configured to operate at 100 MHz and needs to be monitored, CCUCON3.SBPDIV should be written with 0x14 and CCUCON3.SBPSEL with 00B.
This selects a target monitoring frequency of 5 MHz and divides the SPB clock by 20 resulting also in 5 MHz.
If the SPB is configured to operate at 20 MHz and needs to be monitored, CCUCON3.SBPDIV should be written with 0x04 and CCUCON3.SBPSEL with 00B.
If you configure 5MHz for target monitoring frequency, MCU operate to detect SRI clock error as below.
1) -12.41% > or 12.11% < , error is always detected
2) -12.41% ~ -3.9%, error can be detected. It means that error can’t be detected also
3) 2.83% ~ 12.11%, error can be detected. It means that error can’t be detected also
As I checked it, there is no mentioned about above range in TC26x user manual. only available LOWER and UPPER value
The range can be checked from "table 8-4 Target trimmed Check limits" in TC23x user manual.
Jun 16, 2020
02:16 AM
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Jun 16, 2020
02:16 AM
Hello Harvey,
Thanks for the immediate response.
Is there anything to be modified in the software?
If the root cause of this alarm is hardware, then what is the action to be taken?
Thanks for the immediate response.
Is there anything to be modified in the software?
If the root cause of this alarm is hardware, then what is the action to be taken?
Jun 16, 2020
02:26 AM
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Jun 16, 2020
02:26 AM
Hello Harvey,
Thanks for the immediate response.
Is there anything to be modified in the software? The following are the Clock Monitor configurations
* 1.Configured PLL Frequency: 200MHz
* 2.Configured PLLERay Frequency : 80MHz
* 3.Configured SRI Frequency : 200MHz
* 4.Configured SPB Frequency : 100MHz
* 5.Configured GTM Frequency : 100MHz
* 6.Configured STM Frequency : 100MHz
SCU_CCUCON3.U |= 0x00281028;
SCU_CCUCON4.U |= 0x00141414;
If the root cause of this alarm is hardware, then what is the action to be taken?
Thanks for the immediate response.
Is there anything to be modified in the software? The following are the Clock Monitor configurations
* 1.Configured PLL Frequency: 200MHz
* 2.Configured PLLERay Frequency : 80MHz
* 3.Configured SRI Frequency : 200MHz
* 4.Configured SPB Frequency : 100MHz
* 5.Configured GTM Frequency : 100MHz
* 6.Configured STM Frequency : 100MHz
SCU_CCUCON3.U |= 0x00281028;
SCU_CCUCON4.U |= 0x00141414;
If the root cause of this alarm is hardware, then what is the action to be taken?
Jun 16, 2020
05:50 PM
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Jun 16, 2020
05:50 PM
As I mentioned above comments,
For example,
If the SPB is configured to operate at 100 MHz and needs to be monitored, CCUCON3.SBPDIV should be written with 0x14 and CCUCON3.SBPSEL with 00B. I
This selects a target monitoring frequency of 5 MHz and divides the SPB clock by 20 resulting also in 5 MHz
So, if the SRI is configured to operation at 200MHz and needs to be monitored, CCUCON3.SRIDIV should be written with 0x28 and CCUCON3.SRISEL with 00B.
Please check with CCUCON3.SRIDIV (0x28) and CCUCON3.SRISEL (0x0)
Thanks.
For example,
If the SPB is configured to operate at 100 MHz and needs to be monitored, CCUCON3.SBPDIV should be written with 0x14 and CCUCON3.SBPSEL with 00B. I
This selects a target monitoring frequency of 5 MHz and divides the SPB clock by 20 resulting also in 5 MHz
So, if the SRI is configured to operation at 200MHz and needs to be monitored, CCUCON3.SRIDIV should be written with 0x28 and CCUCON3.SRISEL with 00B.
Please check with CCUCON3.SRIDIV (0x28) and CCUCON3.SRISEL (0x0)
Thanks.
Jun 16, 2020
09:32 PM
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Jun 16, 2020
09:32 PM
Hello,
As you mentioned the CCUCON3.SRISEL = 0 and CCUCON3.SRIDIV = 0x28. \
Other than the software configurations is there any hardware malfunction impacts the SRI frequency Out of Range Alarm?
As you mentioned the CCUCON3.SRISEL = 0 and CCUCON3.SRIDIV = 0x28. \
Other than the software configurations is there any hardware malfunction impacts the SRI frequency Out of Range Alarm?
Jun 16, 2020
10:14 PM
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Jun 16, 2020
10:14 PM
I think if external oscillator is unstable, SRI alarm can be occurred according to below conditions
1) -12.41% > or 12.11% < , error is always detected
2) -12.41% ~ -3.9%, error can be detected. It means that error can’t be detected also
3) 2.83% ~ 12.11%, error can be detected. It means that error can’t be detected also
1) -12.41% > or 12.11% < , error is always detected
2) -12.41% ~ -3.9%, error can be detected. It means that error can’t be detected also
3) 2.83% ~ 12.11%, error can be detected. It means that error can’t be detected also
Jun 17, 2020
01:02 AM
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Jun 17, 2020
01:02 AM
Hello,
We faced this issue for the first time.
The software configurations are not the root cause of this alarm. The unstable external oscillator is the root cause of this alarm..Right?
We faced this issue for the first time.
The software configurations are not the root cause of this alarm. The unstable external oscillator is the root cause of this alarm..Right?