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MalolanSrinivas
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Dear Team,

I am verifying the section 15.3.1.2.4 Interface to the Register Monitor under SMU from TC3xx Part1 UserManual v01_00_EN

While executing the test, I always end up with 'No fault' detected in RMEF register (Always 0x00000000). I wish to inject a bit flip in any of these safety flip-flop registers (ex., LBISTCTRL3) so that the corresponding bit (here RMEF[4] for SCU) is set.  Is this possible ? 

So far, I tried to inject a bit flip in MTU module by playing around with ECCD, ECCS registers which affect the MISCERR and OPERR bits in the corresponding FAULTSTS register(ex., CPU0_PMEM). But this does not affect the Register Monitor test in any way.

 

Thank you!

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1 Solution
Di_W
Moderator
Moderator
Moderator
500 solutions authored 1000 replies posted 250 solutions authored

Dear Users,

For 1), the Register Monitor Test mechanism is already a test of a safety mechanism. There is no need to test the test of a safety mechanism
For your 2) question, If you mean you expect some value (e.g 01H) in MCi_FAULTSTS.MISCERR, after setting MCi_ECCS.SFFD. But zero vlaue is showed instead? What shall be the expected self-test results and value in MCi_FAULTSTS.MISCERR?

In SM UM, 5.63 ESM[SW]:LMU.RAM:REG_MONITOR_TEST
Description Application SW shall execute the REGISTER MONITOR test by starting MCi_ECCS.SFFD.
Once started, Application SW shall check that REGISTER_MONITOR test execution time does not exceed expected value.At the end of the test, Application SW shall check self-test results by reading MCi_FAULTSTS.MISCERR.

In TC3xx UM, MCi_FAULTSTS (i=0-95)
Miscellaneous Error Status- MISCERR
One bit status corresponding to each of the error sources contributing to the Miscellaneous Error (ME) alarm. Enabled by ALMSRCS.MISCE. If multiple errors happened, multiple bits are set at the same time. To clear, write '0'. Write of '1' has no effect. Even if any bit is set, further errors are still forwarded. Unspecified bits are reserved for future use and shall always return 0.
01H Failure detected during safety Flip-Flop self test (triggered by setting ECCS.SFFD). The ME alarm is not triggered by this fail.Hence the software shall poll the status of this bit to check if the safety Flip-Flop self test failed.

Answer:

MISCERR[0] will be set only if a real error was detected.
When self test with SFFD is triggered- you should see OPErr[2] set.
Without a real error, MISCERR will be zero.

 

dw

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1 Reply
Di_W
Moderator
Moderator
Moderator
500 solutions authored 1000 replies posted 250 solutions authored

Dear Users,

For 1), the Register Monitor Test mechanism is already a test of a safety mechanism. There is no need to test the test of a safety mechanism
For your 2) question, If you mean you expect some value (e.g 01H) in MCi_FAULTSTS.MISCERR, after setting MCi_ECCS.SFFD. But zero vlaue is showed instead? What shall be the expected self-test results and value in MCi_FAULTSTS.MISCERR?

In SM UM, 5.63 ESM[SW]:LMU.RAM:REG_MONITOR_TEST
Description Application SW shall execute the REGISTER MONITOR test by starting MCi_ECCS.SFFD.
Once started, Application SW shall check that REGISTER_MONITOR test execution time does not exceed expected value.At the end of the test, Application SW shall check self-test results by reading MCi_FAULTSTS.MISCERR.

In TC3xx UM, MCi_FAULTSTS (i=0-95)
Miscellaneous Error Status- MISCERR
One bit status corresponding to each of the error sources contributing to the Miscellaneous Error (ME) alarm. Enabled by ALMSRCS.MISCE. If multiple errors happened, multiple bits are set at the same time. To clear, write '0'. Write of '1' has no effect. Even if any bit is set, further errors are still forwarded. Unspecified bits are reserved for future use and shall always return 0.
01H Failure detected during safety Flip-Flop self test (triggered by setting ECCS.SFFD). The ME alarm is not triggered by this fail.Hence the software shall poll the status of this bit to check if the safety Flip-Flop self test failed.

Answer:

MISCERR[0] will be set only if a real error was detected.
When self test with SFFD is triggered- you should see OPErr[2] set.
Without a real error, MISCERR will be zero.

 

dw

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