Jan 16, 2020
04:03 AM
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Jan 16, 2020
04:03 AM
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Jan 17, 2020
05:26 AM
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Jan 17, 2020
05:26 AM
Hi Lucas,
In the case of the Aurix family, the PFLASH ECC mechanism implements a Safety ECC methodology by default. When PFLASH is erased, both the PFLASH address region and the associated ECC code are erased to a '0' value. An all '0' ECC code is not a validcode for an all '0' PFLASH memory, since the ECC code incorporates more information (as a safety mechanism). If the address is read while in the erased state, then this will generate an ECC error. The same behavior does not apply for erased DFLASH, since the ECC code only considers the data. An all '0' data has a valid ECC code of all '0'.
Best regards,
Mr. AURIX™
In the case of the Aurix family, the PFLASH ECC mechanism implements a Safety ECC methodology by default. When PFLASH is erased, both the PFLASH address region and the associated ECC code are erased to a '0' value. An all '0' ECC code is not a validcode for an all '0' PFLASH memory, since the ECC code incorporates more information (as a safety mechanism). If the address is read while in the erased state, then this will generate an ECC error. The same behavior does not apply for erased DFLASH, since the ECC code only considers the data. An all '0' data has a valid ECC code of all '0'.
Best regards,
Mr. AURIX™