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AURIX™ Forum Discussions

User9635
Level 4
Level 4
50 replies posted 50 questions asked 25 replies posted
‎May 19, 2020 12:37 PM
‎May 19, 2020 12:37 PM

RSTSTAT SMU Bit and TRAPSTAT SMUT Bit difference in Aurix 2G

Hello Support,

Can you please tell me under what condition RSTSTAT.SMU Bit 3 will be SET?
Can you please tell me under what condition TRAPSTAT.SMUT Bit 4 will be SET?
Will they both be SET together when SMU Alarm Configuration is either NMI [0x5] or RESET [0x6] or Interrupt [0x2, 0x3, 0x4]?
Will any of the above two bits will be set when all SMU Alarm Configurations are 0x0 or 01 [Inactive or Idle]?
May be you can provide me a decision table for conditions under which above two bits will be SET.
4327.attach

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