RESET after code to start OS Sch table or non-volatile mem read add in INIT task

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cross mob
Level 1
Level 1

I am currently having reset on my system after I added code to start schedule table. although this reset occurs even before the code to start schedule table is executed.
I have activated all the 3 cores on my machine now I am not sure which core is reseting the system and why.

I have checked RSTSTAT register it shows "SW" reset was requested and RSTCON register shows "System" but this is always active I think and RSTCON2.USRINFO is always 0.

I have set breakpoints in trap routines and none of the TRAP were triggered so this does not seem to be related to context switch area. What else could be possible?
I want to know what is the cause of reset or at least on which core and at what location this reset occurs, any help in this direction would be of great help.

PS:I also had a condition where I had put break point (probably in ISR) after which code would run normally (or as expected). Also note all the 3 WDGs is disabled in Lauterback script

2 Replies
Level 6
Level 6
10 likes received 10 solutions authored 5 solutions authored
It's almost certainly something to do with the watchdog system - by default, if a watchdog recovery timer expires, it causes a reset. You might try changing the SMU configuration to ignore the recovery timer alarms instead of doing a reset by changing ALM10[16] and ALM10[17] to no action (SMU_AG10CFG1=0 and SMU_AG10CFG2 = 0).

By default, when a debugger is connected, the watchdog system is disabled. If you have "SYStem.Option WDTSUS ON" in a Lauterbach script, it will enable the watchdog system, but suspend it if the CPU is suspended (e.g., at a breakpoint). Is WDTSUS in your scripts?

In addition to the CPU watchdogs, there's also an overall Safety Watchdog to think about.
50 likes received 500 replies posted 100 solutions authored
RSTSTAT.B.SW will be set only when the last reset was done because of a write of 0x2 to register SWRSTCON. Please check your code under which circumstances a write to this register occurs. In the debugger you can set a write breakpoint to the address of SWRSTCON to detect the write to this register. Watchdog reset is visible as SMU reset.