RAM Test in TC233_LP

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Punyashree_R
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First reply posted 5 sign-ins First question asked

I am trying to perform the RAM test for TC233_LP controller for CPU0DSPR by using the example code of MTU_MBIST_1_KIT_TC297_TFT example code. But I am facing the Trap issue, I have attached the trap details and where i am facing the trap issue. I have called RAM test function in cpu0_main. Kindly help me to resolve the issue.

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Meet_T
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25 likes received 50 solutions authored 100 replies posted

Hi @Punyashree_R ,

 

Based on the architecture manual the trap class 1, trap id 5 is for  Memory Protection Peripheral Access Trap which is triggered when A program executing in User-0 mode attempts a load or store access to a segment is configured to be a peripheral segment. Please refer to page number - 78 in Architecture User Manual for more details.

 

According to this can you please check if you are changing anything in the example code that changes the execution mode to User-0 mode and therefore triggering the trap. Also, from trapinfo you can check the taddr and see which instruction is triggering this trap.

 

Best Regards,

Meet.

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Meet_T
Moderator
Moderator
Moderator
25 likes received 50 solutions authored 100 replies posted

Hi @Punyashree_R ,

 

Based on the architecture manual the trap class 1, trap id 5 is for  Memory Protection Peripheral Access Trap which is triggered when A program executing in User-0 mode attempts a load or store access to a segment is configured to be a peripheral segment. Please refer to page number - 78 in Architecture User Manual for more details.

 

According to this can you please check if you are changing anything in the example code that changes the execution mode to User-0 mode and therefore triggering the trap. Also, from trapinfo you can check the taddr and see which instruction is triggering this trap.

 

Best Regards,

Meet.

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