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nsyed
Level 5
First solution authored 25 sign-ins 100 replies posted
Level 5

Hello,

I have configured GTM_ATOM0_CH5_CTRL.RST_CCU0 = 1 (Trigger TRIG_[4]), when I set
GTM_ATOM0_CH4_CM0 = GTM_ATOM0_CH5_CM0 = 000186A0 (Frequency Ticks/Counts required for my application) and GTM_ATOM0_CH5_CM1 = 0 (0% duty cycle), I see the PWM output is always commanded high.

I am wondering about this behaviour, my expectation was that the PWM output will be low.

I went through the Section 28.15.3.3.1 of the Reference manual which talks about the behaviour of CNO, CM0 & CM1 when CN0 is reset by the trigger from another channel.
From this section Iwhen CNO is reset (by Trigger TRIG_[4]) it becomes equal to CM1 (0) and should immediately become low.

Could you please clarify what is going on in this case ? Any work-around to overcome this problem ?

 

Adding another observation, When i keep rest of the configuration same and change GTM_ATOM0_CH5_CTRL.RST_CCU0 = 0 (Matching comparison with  CM0), the PWM output becomes low 

 

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1 Solution
ugo_8a
Employee
10 solutions authored 25 sign-ins 25 replies posted
Employee

Hi , I did some testing and I think I know what is the problem, as mentioned in the user manual if you want to have a 0% duty cycle when RSR_CCU0= 1 you need to set CM0 > MAX

but you can also test and get  the pin set to low when you set  CM0 to CM1+1 (also do not forget to set the GTM_TOM0_TGC0_FUPD_CTRL.B.FUPD_CTRL1 = 2;)

to explain a little bit more how the edges are generated when RSR_CCU0= 1 please see the attached excel sheet. 

 

 

 

ugo_8a_0-1657641106196.png

finally this is the code I ran on my test (I used TOMs because I have some limitations in the pin selection on my HW but the code should work for ATOMs)

 

 

 

void GTM_TOM_init(void)
{


   /*configure output to TOM alternate function*/
   P02_IOCR0.B.PC0 = 0x11;      //P02.0
   P02_IOCR8.B.PC9 = 0x11;      //P02.9



/// CH0

   /*TOM0 Channel 0 is Reset */
   GTM_TOM0_TGC0_GLB_CTRL.B.RST_CH0    = 1;
   /*TOM0 Channel 0 is Enabled*/
   GTM_TOM0_TGC0_GLB_CTRL.B.UPEN_CTRL0    = 2;

   GTM_TOM0_TGC0_FUPD_CTRL.B.RSTCN0_CH0    = 0;

   /*Force Update to TOM0 CH0*/
   GTM_TOM0_TGC0_FUPD_CTRL.B.FUPD_CTRL0   = 2;
   /*Select CMU CLK0*/
   GTM_TOM0_CH0_CTRL.B.CLK_SRC_SR         = 0;

   /*Route compare match to TRIG_[x] signal*/
   GTM_TOM0_CH0_CTRL.B.TRIGOUT         = 1; //Expose trigger signal to TOM0_1

   /*Enable Channel on Update Trigger, via SR0/1*/
   GTM_TOM0_TGC0_ENDIS_CTRL.B.ENDIS_CTRL0  = 2;
   /*Enable Channel Output on Update Trigger, via SR0/1*/
   GTM_TOM0_TGC0_OUTEN_CTRL.B.OUTEN_CTRL0    = 2;



   /*Set Period */
   GTM_TOM0_CH0_SR0.U      = 5000;
   /*Set  Duty*/
   GTM_TOM0_CH0_SR1.U      = 2500;

   /*Set TOUT Wrapper*/
   GTM_TOUTSEL0.B.SEL0     = 4; //TOM0_CH0 P02.0
   //use internal trigger
//   GTM_TOM0_TGC0_INT_TRIG.B.INT_TRIG0 = 2;
//
//   GTM_TOM0_CH0_CTRL.B.EXT_TRIG  = 1;       //Signal TIM_EXT_CAPTURE(x) as trigger
//
//   // we need to send the TIM(x)EXTCAPTURE to the TGC via TRIGOUT
//   GTM_TOM0_CH0_CTRL.B.EXTTRIGOUT = 1;


///CH1



   /*TOM0 Channel 1 is Reset */
   GTM_TOM0_TGC0_GLB_CTRL.B.RST_CH1    = 1;
   /*TOM0 Channel 1 is Enabled*/
   GTM_TOM0_TGC0_GLB_CTRL.B.UPEN_CTRL1    = 2;

   /*Force Update to TOM0 CH1*/
   GTM_TOM0_TGC0_FUPD_CTRL.B.FUPD_CTRL1   = 2;
   GTM_TOM0_TGC0_FUPD_CTRL.B.RSTCN0_CH1   = 0;
   /*Select CMU CLK0 as Clock*/
   GTM_TOM0_CH1_CTRL.B.CLK_SRC_SR         = 0;

  // GTM_TOM0_CH1_CTRL.B.SL              = 0; //Do not invert signal level

   /*Reset counter on TRIG[x-1]*/
   GTM_TOM0_CH1_CTRL.B.RST_CCU0        = 1; //Reset counter on trigger from TOM0_0

   /*Enable Channel on Update Trigger, via SR0/1*/
   GTM_TOM0_TGC0_ENDIS_CTRL.B.ENDIS_CTRL1  = 2;
   /*Enable Channel Output on Update Trigger, via SR0/1*/
   GTM_TOM0_TGC0_OUTEN_CTRL.B.OUTEN_CTRL1    = 2;

   /*Set Period */
   GTM_TOM0_CH1_SR0.U      = 5001;
   /*Set  Duty*/
   GTM_TOM0_CH1_SR1.U      = 5000;

   /*Set TOUT Wrapper*/
   GTM_TOUTSEL14.B.SEL4     = 6; // P02.9
   GTM_TOM0_CH1_CTRL.B.RST_CCU0 = 1;



   GTM_TOM0_TGC0_GLB_CTRL.B.HOST_TRIG = 1;


}

 

 

 

 

 

 

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14 Replies
nsyed
Level 5
First solution authored 25 sign-ins 100 replies posted
Level 5

Folks, 

Is this expected behavior or is there any existing errata ?

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nsyed
Level 5
First solution authored 25 sign-ins 100 replies posted
Level 5

Dear Community Members,

Any thoughts on the issue I am facing ?

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nsyed
Level 5
First solution authored 25 sign-ins 100 replies posted
Level 5

Dear Community Members, 

 

Any thoughts on this issue ? Is there any errata to explain the behavior which I am experiencing ?

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nsyed
Level 5
First solution authored 25 sign-ins 100 replies posted
Level 5

Dear Infineon Team, 

Could you please look into this issue? I would appreciate any feedback on this topic.

 

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ugo_8a
Employee
10 solutions authored 25 sign-ins 25 replies posted
Employee

Hi , looking at your configuration that is the expected behavior, for example by default the (A)TOM channel SL is 1 so if you take a look at the diagram below  once you enable the channel the output should start low and remain at that level until CN0 matches CM1, however because in your configuration CM1 is "0" the match occurs immediately so a rising edge is generated, then CN0 continues to go up and you would expect that the pin goes low at CM0 however at the same time the trigger signal is generated from the previous channel and resets CN0 so now CN0 is again "0" and  matches CM1 so the output never had a chance to go low

 

ugo_8a_1-1657221067041.png

 

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nsyed
Level 5
First solution authored 25 sign-ins 100 replies posted
Level 5

Hello,

In my configuration, I have set UDMODE = 0b00 (up/down counter mode disabled: CN0 counts always up) & not Up-Down mode.  I am expecting below behavior, based on the datasheet

when SL = 1 & CN0 reset, it matches with the CM1 value and should always remain 0.  Could you please clarify ?

nsyed_0-1657238509830.png

 

nsyed_1-1657238551362.png

 

 

 

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ugo_8a
Employee
10 solutions authored 25 sign-ins 25 replies posted
Employee

Hello, 

when SL = 1 the idle state is "0" then when CN0 match CM1 the pin goes "high". so no you wont see the pin low when SL=1 CN0 is reset and CM1 is zero.

Note: you might see the pin level set to high after reset, because the default state of some pins is defined by pin HWCFG[6] (P14.4), then the ATOM takes over and might change the state of the pin.

will be helpful if you can share a timing diagram of ATOM_CH4 and ATOM_CH5 and what kind of signal are you trying to archive.

BR

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nsyed
Level 5
First solution authored 25 sign-ins 100 replies posted
Level 5

Hello Ugo,

Thanks for so much for your support.

Your comment regarding, when SL = 1 - when CN0 match CM1 the pin goes "high" is not inline with the Figure 76 of the User manual.
In the Figure 76 (above snapshot),

when SL = 1 - when CN0 match CM1 the pin goes "low"

I am seeing this behaviour all the time and not just after reset, even after configuration of ATOM.

I am attaching my register configuration. 

I contacted local Infineon design house and they can reproduce this issue, however we cannot root-cause what is causing this issue and seem to think there should be some errata for this behaviour.

Is it possible for you to create some sample code and test this behaivour on your end to confirm this issue ?

 

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ugo_8a
Employee
10 solutions authored 25 sign-ins 25 replies posted
Employee

Hello , 

my apologies, you are correct, I was looking at the wrong diagram, let me take a look again and try to reproduce the behavior, so far the errata only mentions an issue when one-shot mode is used OSM but  let me take a look again. 

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nsyed
Level 5
First solution authored 25 sign-ins 100 replies posted
Level 5

Hello Ugo,

Thank you for checking this. Please try this configuration once when you get chance and let me know your findings.
Yes you are correct, I went through the Errata and did not find anything specific to the SOMP continuous mode.

It will be helpful if this behavior can be confirmed and any work-around is proposed by experts from Infineon's team.

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ugo_8a
Employee
10 solutions authored 25 sign-ins 25 replies posted
Employee

Hi , I did some testing and I think I know what is the problem, as mentioned in the user manual if you want to have a 0% duty cycle when RSR_CCU0= 1 you need to set CM0 > MAX

but you can also test and get  the pin set to low when you set  CM0 to CM1+1 (also do not forget to set the GTM_TOM0_TGC0_FUPD_CTRL.B.FUPD_CTRL1 = 2;)

to explain a little bit more how the edges are generated when RSR_CCU0= 1 please see the attached excel sheet. 

 

 

 

ugo_8a_0-1657641106196.png

finally this is the code I ran on my test (I used TOMs because I have some limitations in the pin selection on my HW but the code should work for ATOMs)

 

 

 

void GTM_TOM_init(void)
{


   /*configure output to TOM alternate function*/
   P02_IOCR0.B.PC0 = 0x11;      //P02.0
   P02_IOCR8.B.PC9 = 0x11;      //P02.9



/// CH0

   /*TOM0 Channel 0 is Reset */
   GTM_TOM0_TGC0_GLB_CTRL.B.RST_CH0    = 1;
   /*TOM0 Channel 0 is Enabled*/
   GTM_TOM0_TGC0_GLB_CTRL.B.UPEN_CTRL0    = 2;

   GTM_TOM0_TGC0_FUPD_CTRL.B.RSTCN0_CH0    = 0;

   /*Force Update to TOM0 CH0*/
   GTM_TOM0_TGC0_FUPD_CTRL.B.FUPD_CTRL0   = 2;
   /*Select CMU CLK0*/
   GTM_TOM0_CH0_CTRL.B.CLK_SRC_SR         = 0;

   /*Route compare match to TRIG_[x] signal*/
   GTM_TOM0_CH0_CTRL.B.TRIGOUT         = 1; //Expose trigger signal to TOM0_1

   /*Enable Channel on Update Trigger, via SR0/1*/
   GTM_TOM0_TGC0_ENDIS_CTRL.B.ENDIS_CTRL0  = 2;
   /*Enable Channel Output on Update Trigger, via SR0/1*/
   GTM_TOM0_TGC0_OUTEN_CTRL.B.OUTEN_CTRL0    = 2;



   /*Set Period */
   GTM_TOM0_CH0_SR0.U      = 5000;
   /*Set  Duty*/
   GTM_TOM0_CH0_SR1.U      = 2500;

   /*Set TOUT Wrapper*/
   GTM_TOUTSEL0.B.SEL0     = 4; //TOM0_CH0 P02.0
   //use internal trigger
//   GTM_TOM0_TGC0_INT_TRIG.B.INT_TRIG0 = 2;
//
//   GTM_TOM0_CH0_CTRL.B.EXT_TRIG  = 1;       //Signal TIM_EXT_CAPTURE(x) as trigger
//
//   // we need to send the TIM(x)EXTCAPTURE to the TGC via TRIGOUT
//   GTM_TOM0_CH0_CTRL.B.EXTTRIGOUT = 1;


///CH1



   /*TOM0 Channel 1 is Reset */
   GTM_TOM0_TGC0_GLB_CTRL.B.RST_CH1    = 1;
   /*TOM0 Channel 1 is Enabled*/
   GTM_TOM0_TGC0_GLB_CTRL.B.UPEN_CTRL1    = 2;

   /*Force Update to TOM0 CH1*/
   GTM_TOM0_TGC0_FUPD_CTRL.B.FUPD_CTRL1   = 2;
   GTM_TOM0_TGC0_FUPD_CTRL.B.RSTCN0_CH1   = 0;
   /*Select CMU CLK0 as Clock*/
   GTM_TOM0_CH1_CTRL.B.CLK_SRC_SR         = 0;

  // GTM_TOM0_CH1_CTRL.B.SL              = 0; //Do not invert signal level

   /*Reset counter on TRIG[x-1]*/
   GTM_TOM0_CH1_CTRL.B.RST_CCU0        = 1; //Reset counter on trigger from TOM0_0

   /*Enable Channel on Update Trigger, via SR0/1*/
   GTM_TOM0_TGC0_ENDIS_CTRL.B.ENDIS_CTRL1  = 2;
   /*Enable Channel Output on Update Trigger, via SR0/1*/
   GTM_TOM0_TGC0_OUTEN_CTRL.B.OUTEN_CTRL1    = 2;

   /*Set Period */
   GTM_TOM0_CH1_SR0.U      = 5001;
   /*Set  Duty*/
   GTM_TOM0_CH1_SR1.U      = 5000;

   /*Set TOUT Wrapper*/
   GTM_TOUTSEL14.B.SEL4     = 6; // P02.9
   GTM_TOM0_CH1_CTRL.B.RST_CCU0 = 1;



   GTM_TOM0_TGC0_GLB_CTRL.B.HOST_TRIG = 1;


}

 

 

 

 

 

 

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nsyed
Level 5
First solution authored 25 sign-ins 100 replies posted
Level 5

Hello Ugo, 

Thank you for the explanation and example. I will go through example and let you know.

Appreciate your help!!!

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nsyed
Level 5
First solution authored 25 sign-ins 100 replies posted
Level 5

Hello Infineon Team, 

Any feedback on this topic ?

 

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nsyed
Level 5
First solution authored 25 sign-ins 100 replies posted
Level 5

Hello Infineon Team, 

Is there any Errata to explain this behaviour ? 

 

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