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User16898
Level 4
Level 4
Hi,

I have problem with QSPI module in TC222L16F133FACKXUMA1 microcontroller.
After some time (around 30 to 60 minutes) polling data from bms controller LTC6813 I receive messages which first two bytes are always 0xFF
(while, under oscilloscope those bytes are clearly not 0xFF),
Along with that problem, few error flags occurs:
rxFifoOverflowError and expectTimeoutError.
After inspecting user manual, first error should appear as stated on picture below:

4395.attach
Questions:

FPI is too slow nad baundrate is very high - what are those too slow and very high frequencies, or what ratio between them should be kept ? Its not mentioned anywhere in User manual.

Is there any way to control FPI frequency and make it higher? The user manual says, that there is no clock control register in TC22x and TC23x for this bus.

Is there any way to overcome this problem beside decreasing QSPI frequency (we currently operate on 1MHz)? Is this problem somehow connected to the second mentioned error flag (expectTimeoutError)?

Our current QSPI module works on interrupts without DMA.
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7 Replies
cwunder
Employee
Employee
10 likes given 100 solutions authored 5 likes given
Have you created the QSPI driver?

The FPI is the SPB in this implementation. This can run up to 1/2 the frequency of the SRI (133MHz) on this device.
The QSPI depends on both the frequency of the SPB and BAUD2. You can find the dividers in the CCUCON0 register.

What frequencies do you have for the SRI / SPB / BAUD2?
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User16898
Level 4
Level 4
I'm not really sure how should I calculate the frequency you asked for, here are screenshots of startup registers I managed to capture:

4431.attach

4432.attach

4433.attach

4434.attach

4435.attach

4436.attach

From what I understand, SPB is now two times faster than baud2, but from what i can see is that after baud2 there is also some kind of divider from PLLCON0. How all that is connected?
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cwunder
Employee
Employee
10 likes given 100 solutions authored 5 likes given
Your clock settings do not appear to be correct. Where did you get the code for configuring the PLL and clock dividers?

It says you have selected the PLL as the clock source for fsource however you have the SCU_CCUCON1.INSEL = fBACK (100MHz), you did not include the SCU_PLLSTAT to know more. You have P=0, K2=15 and N=99. The PLL formula in normal is = N/(P*K2)*fOSC.

The fPLLVCO = fOSC*N/P and its limits must result in a frequency between 400MHz to 800MHz.

Here are the clock settings from the BiFaces for 133.33MHz on the PLL when using a 20MHz OSC (TC233).

4439.attach
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User16898
Level 4
Level 4
I changed all the register to the values you have provided, it kinda worked but i found another problem, multican module stopped working properly, no frames are sent on multican, only this is visible on scope:

4451.attach

After changing all the register using your values, my fpllVCO is equal 800Mhz and pll 133.33

pllstat is here:

4452.attach

After digging into user manual and ILLD, i found out, that multican freq for fCLC is fSPB

Fragment of ILLD, IfxMultican_Can.c, line 997

/* Select the clock input, two writes to the CLKSEL are always necessary */
IfxMultican_setInputClock(mcanSFR, IfxMultican_ClockSelect_noClock);
IfxMultican_setInputClock(mcanSFR, IfxMultican_ClockSelect_fclc); /* Selects Fclc = Fspb */

fSPB from values written into CCUCON0 is fsource/2 which is 66MHz ( am I right?)
fCAN is now 66MHz as well.

I am using only 1 node, baudrate is 125000 and I have 16 message objects, so 12MHz for both is enough, am I right?

Obviously CAN was working before all those changes in registers
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User16898
Level 4
Level 4
I changed all the register to the values you have provided, it kinda worked but i found another problem, multican module stopped working properly, no frames are sent on multican, only this is visible on scope:

4451.attach

After changing all the register using your values, my fpllVCO is equal 800Mhz and pll 133.33

pllstat is here:

4452.attach

After digging into user manual and ILLD, i found out, that multican freq for fCLC is fSPB

Fragment of ILLD, IfxMultican_Can.c, line 997

/* Select the clock input, two writes to the CLKSEL are always necessary */
IfxMultican_setInputClock(mcanSFR, IfxMultican_ClockSelect_noClock);
IfxMultican_setInputClock(mcanSFR, IfxMultican_ClockSelect_fclc); /* Selects Fclc = Fspb */

fSPB from values written into CCUCON0 is fsource/2 which is 66MHz ( am I right?)
fCAN is now 66MHz as well.

I am using only 1 node, baudrate is 125000 and I have 16 message objects, so 12MHz for both is enough, am I right?

Obviously CAN was working before all those changes in registers
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cwunder
Employee
Employee
10 likes given 100 solutions authored 5 likes given
You will also need to adjust your CAN timing since it changed.

Using 1 CAN node and 16 message objects only requires 12MHz on the fCLC (which is the same for the fSPB) for 1MBaud. You are at 125Kbaud so no issue.
However, for getting the correct CAN baud rate you usually need a clock that is evenly divisible by 4. I would suggest that you use the fOSC or change the fPLL to be 128MHz (since the fERAY is not available on your device) for the fCAN clock..
4471.attach
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User16898
Level 4
Level 4
Thanks for response.
I changed my PLL setting to receive fPLL equal to ~120Mhz
My startup registers are:
SBCU_CON : 0xff09ffff
DCON0: 0x0
PCON0: 0x0
GTM_CLC: 0x0

FLASH0_FCON: 0x910000
SCU_CCUCON0: 0x1120148
SCU_CCUCON1: 0x2211
SCU_CCUCON2: 0x2
SCU_OSCCON: 0x10
SCUPLLCON0: 0x101fe00
SCUPPLCON1: 0x4020f

fOSC is 133.33. and
fPLL parameters( from datasheet) are
N = 8 ( Aurix takes N + 1 for calculation)
P = 1 (Aurix takes P + 1 for calculation)
K1 = 4 (Aurix takes K1 + 1 for calculation)

formula with above parameters:
fPLL = (N/ P* K1) * fOSC

will give fPLL = ~120Mhz(119,7Mhz)
which is divisible by 4.

Unfortunetelly CAN is still not working.
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