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AURIX™ Forum Discussions

User16280
Level 1
Level 1
Hi Reader,

After loading the data into Tx FIFO(Data entry register 0), i am unable to see the content on debugger. I am skeptical whether the data has been loaded or not. Any suggestions to check this?
However i am considering to check the SPI lines at channel level with a logic analyser.

Spi_Regs->Bacon_Entry_Reg = (0 << 28/*CS*/)|(0 << 21/*MSB*/)|(1 << 0/*LAST*/)|(7 << 23/*DL*/);
uint32 buf = 0xCC;
Spi_Regs->Data_Entry_Reg0 = buf;
uint32 buf_1=0x00;
buf_1 = *(uint32*) 0xF0001D90;

Thanks in advance!!!
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MoD
Employee
Employee
25 likes received 50 solutions authored 100 sign-ins
You can't read the TX FIFO. The DATAENTRY register is a write only register. If yiu read the RXEXIT register then you get the next available value from the receive FIFO if there is anything available.
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