Hello All,
I am trying to understand the iLLD example code of QSPI CPU TC277. When i was investingating the below code
My Queries,
1) My Buffer size is 4 bytes - Given the job "count is 3" form the code I would like to understand, How can the last byte will be transmitted into the HW buffer(1 Bacon + 3 byte ) on the same transmission window.
2) Does the transmit and Receive ISR enabled after the buffer is filled according to the code.
IfxQspi_SpiMaster_exchange() calls IfxQspi_SpiMaster_write() to write the data. // This is the starting point of the SPI transfer
IfxQspi_SpiMaster_write() calculates the available FIFO size which is 4, minus 1 for the BACON configuration data.
Ifx_SizeT count = (Ifx_SizeT)(IFXQSPI_HWFIFO_DEPTH - 1 - IfxQspi_getTransmitFifoLevel(qspiSFR)); // -1, since BACON allocates one FIFO entry
count = __min(job->remaining, count);
...
(count == 3 at this point)
if (count > 0)
{
job->remaining = job->remaining - count;
// we have to push another BACON into FIFO before the last data word
boolean lastWrite = (job->remaining == 0) ? TRUE : FALSE;
boolean interruptState;
if ((chHandle->firstWrite == TRUE) && (count > 1) && (job->remaining != 0))
{
interruptState = IfxCpu_disableInterrupts(); //In my case Interrupt disabled
}
else
{
......
}
I am not using DMA, so it writes the BACON to the FIFO:
...
IfxQspi_writeBasicConfigurationBeginStream(qspiSFR , chHandle->bacon.U);
...
It then writes 3 bytes into the FIFO:
...
IfxQspi_write8(qspiSFR, cs, job->data, count);
...
then it restores the interrupts and exits out of the function:
...
IfxCpu_restoreInterrupt
Many thanks,
Regards,
Deepak
