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Hi community, @cwunder
May I know the possible reasons for BACON in QSPI module of TC387 not getting updated when using a 16bit channel and the same configuration works fine if the channel is 8 bit.
Regards,
Prathibha
Solved! Go to Solution.
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Thank you all for the feedback. I was able to solve my issue. It was related to data alignment. For 16 bit and 32 bit data transfer the structure in Spi driver needs to be word aligned.
@User22868 Your findings are correct. Until the DATAENTRY, bacon values are not reflected. Same in my case.
In my case, when the data was taken to be written to DATENTRY, I was getting an OS trap for Alignment issue at this point.
So when I debugged found that the Spi driver uses memory mapping and requires the source and destination buffer to be word aligned. I was using the wrong Memmap file.
Thank you for supporting. With your help now I have a better understanding of the issue.
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I would not expect that you would have the same BACON configuration with a frame for 8-bit data width and a frame for 16-bit data width.
You cannot directly write to the BACON register and the value reflects the last transfer that happened on the QSPI. To change a QSPI configuration you must write the new configuration value (BACON value) to either the MIXENTRY or BACONENTRY registers (depending on the mode you are operating on). All writes go through the TXFIFO (as shown below). Following the QSPI rules the BACON value is applied to your transfer and reflected in the BACON register.
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Thank you for the reply @cwunder .
To detail the issue, the driver code has a local lbacon variable which writes to the BACONENTRY. The values are coming till the lbacon variable but the write to bacon is not happening. Is there anything to do with TXFIFO when 16 bit writes are performed?
Attaching a screenshot of the lbacon
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Sorry but I don't understand your issue...
I made a quick example to send on QSPI3 three data transfers. The first transfer is on SLSO3 with 8 data byes in the frame. Followed by a data transfer on SLSO4 with 16 data bytes in the frame. Finally a data transfer on SLSO8 with 32 data bytes in the frame.
You only need to make sure there is room in the TXFIFO before you write to either the BACONENTRY or DATAENTRYx registers.
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I think I am facing a similar issue in my project. When I write my configuration value to BACONENTRY register, the values are not reflecting in BACON register.. unless I write some value to DATAENTRY as well. My MCU is TC367. Exactly, at which point TxFIFO will shift the configuration values to BACON? As soon as the BACONENTRY is written??
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The TXFIFO is keeping track of data or configuration as you write it. The QSPIx_BACON register will update as soon as it is consumed by the QSPI state machine (when using the BACONENTRY and DATAENTRYx registers, if you use the MIXENTRY you must follow the rules of the QSPI).
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@cwunder Thank you for your feedback. In my project, I have an Init function (e.g: Spi_Init) which is triggered only once during the initialization sequence and a periodic runnable (e.g: Spi_Tx) that triggers say every 1ms. In my init function, I initialize my QSPI module by updating GLOBALCON, GLOBALCON1 and BACONENTRY, ECON2, SSOC registers. And in my periodic function, I update DATAENTRY register to trigger the SPI communication. Please find my attached code snippet. What I am experiencing is that, unless my periodic function is triggered atleast once and execute the code where I copy the my RAM data into DATAENTRY register, BACON register values are not reflecting the values that I used in my init function (I'm using Trace-32 to confirm this).
I.e. for example, if I disable the code where I update DATAENTRY register in my periodic function, BACON register never gets updated with BACONENTRY register values that I used in my INIT function.
I may have been missing some point here.... because, I am expecting BACON register to be updated after the my init function is executed... and that it doesnt have to wait for DATAENTRY to be written atleast once... Can you please help me understand from this perspective?
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The BACON (configuration) entry is pending until the next "data entry" occurs. See the description from the user's manual below:
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@cwunder Thank you for the clarification. I did look at this part of the datasheet, but perhaps I didn't understand it the way you explained. Appreciate your feedback.
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Thank you all for the feedback. I was able to solve my issue. It was related to data alignment. For 16 bit and 32 bit data transfer the structure in Spi driver needs to be word aligned.
@User22868 Your findings are correct. Until the DATAENTRY, bacon values are not reflected. Same in my case.
In my case, when the data was taken to be written to DATENTRY, I was getting an OS trap for Alignment issue at this point.
So when I debugged found that the Spi driver uses memory mapping and requires the source and destination buffer to be word aligned. I was using the wrong Memmap file.
Thank you for supporting. With your help now I have a better understanding of the issue.