AURIX™ Forum Discussions

[User16286]

I'm trying to change the SCU clock divider for the QSPI module to get a higher SPI clock rate.
I tried to change it the straightforward way, e.g.

SCU_CCUCON0.B.BAUD2DIV = 1;

But this triggers a trap 4.
What's the right way to do this?

Toshi

[cwunder]

The AURIX has a concept of access protection for the SFR's. When you want to write to a SFR you need to check the access rights.

You can find the access terms defined in a table in the user's manual


For the CCUCON0 register it has SE SV and P for a write.



Typically the SCU write protection (ACCEN) will be configured so that only restricted “Safety” CPU(s) can configure system-critical functionality. This includes the ability to service the Safety Watchdog. In addition, Safety Watchdog disable/enable/configuration function requires a Safety ENDINIT password.

To update the CCUCON0 you must clear the ENDINIT bit for the Safey Watchdog and also write it with the UP bit set to 1. Note: The UP bit will cause a new complete parameter set to be transferred to the CCU. All three registers CCUCON0, 1 and 5 content is taken by CCU.

uint16_t safetyWdtPassword = IfxScuWdt_getSafetyWatchdogPassword();
    
IfxScuWdt_clearSafetyEndinit(safetyWdtPassword);
/* your code to modify SCU_CCUCON0,1 and 5*/
/* read, mask, and set the UP bit if this is the only changes  */
IfxScuWdt_setSafetyEndinit(safetyWdtPassword);

[User16286]

Ah, I tried something similar but forgot to put the register write between the clear and set.
Thanks, it works!

Toshi

[cwunder]

That's great,

I did however forget to say you also need to check the status of the CCUCONx.LCK bit. You can only update the SFR if this is equal to 0.

[User18665]

Hi collegues,
I has a similar problem, when I try to write CCUCON0 register using the DAP interface. Each time I get writing error. Are there any special conditions for DAP ( for SFR writing )?
As I understood, the ACCEN register is in all "1" by default, so, writing ia permitted.