Announcements

Help us improve the Power & Sensing Selection Guide. Share feedback

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
User9635
Level 4
Level 4
50 replies posted 50 questions asked 25 replies posted
Hello Support,

For each cores, there are CPUx_COMPAT [CSFR offset 0x9400] and CPUx_SYSCON [CSFR offset 0xFE14] which are Safety ENDINIT protected in Aurix 1G and Aurix 2G
In order to update these above registers from default Cold Power On RESET values, each core need to modify Safety Watchdog related registers because Safety ENDINIT is already SET.
The code to clear the Safety ENDINIT bit is having multi-core barrier correctly implemented.
There are no RENDEZVOUS/Synchronization error in the code where each cores can serially access the Safety Watchdog registers to CLEAR/SET ENDINIT bit.
Question is, architecturally, each core write accessing Safety Watchdog Registers is allowed by silicon design or only Core 0 should be write accessing Safety Watchdog registers?
Which one is correct by Silicon Design?
I couldn't find anything in the Aurix 2G User Manual, which prohibits Safety Watchdog Register write access by any other core than Core 0.
Please provide detailed snippets of User Manual regarding the correct procedure for this design.
I am assuming the architecture is same for Aurix 1G as well as Aurix 2G and neither User Manual mentions that only Core 0 can write access Safety Watchdog Registers.
Best Regards
0 Likes
3 Replies
NeMa_4793301
Level 6
Level 6
10 likes received 10 solutions authored 5 solutions authored
By default, there is no restriction on which CPU can write to the Safety Watchdog. The TC3xx adds the ability to restrict which bus masters can manipulate the Safety Watchdog.

Ideally, initializing Safety-ENDINIT protected registers should only be performed by one core. Synchronizing access to the Safety Watchdog across multiple cores is fraught with peril.

Why not just initialize the other CPU registers from CPU0, before you bring them out of idle?


6.7.1 CSFR and SFR base Locations
A CPU must access its own CSFR registers using MTCR and MFCR instructions. CSFR registers of other CPUs may be accessed using load and store instructions via the XBAR_SRI.
0 Likes
User9635
Level 4
Level 4
50 replies posted 50 questions asked 25 replies posted
Hello Support,

Can you please provide me the revision and title of the document which contains the above mentioned "Section 6.7.1" contents?
Best Regards
0 Likes
NeMa_4793301
Level 6
Level 6
10 likes received 10 solutions authored 5 solutions authored
I pulled that from tc23x_tc22x_um_v1.1.pdf, but the same text is present in every AURIX User Manual.

In the TC3xx, it's in AURIXTC3XX_um_part1_v1.4.pdf, 5.3.6.1.2 CSFR and SFR base Locations.
0 Likes