Period of Fault Signaling Protocol [SMU_FSP] during Fault Free State

[User9635]

Hell Support,
For Aurix 2G devices, In the revision 1.4 User Manual Part 1, there is
"Figure 167 Time switching protocol"
related to SMU Fault Signaling Protocol.

In the above mentioned figure, Tsmu_ffs [Period of 50% waveform] is determined by "TFSP_HIGH & TFSP_LOW" field value of SMU_FSR Register.
Is the correct statement?

or "TFSP_HIGH & TFSP_LOW" value determines Tsmu_ffs /2 [that means the high duration of the waveform]?

Which one is the correct statement above?

"TFSP_HIGH & TFSP_LOW" -- means concatenated total value of fBack/PRE2 clock ticks. I am assuming this is correct.

Best Regards

[NeMa_4793301]

Neither is correct. Tsmu_ffs is based on the PRE2 divider and is always 50% duty cycle. See Figure 164: Tsmu_ffs is based on PRE2, and Tsmu_fs is based on TFSP_HIGH + TFSP_LOW + 1.

[User9635]

Hello Support,

That means there is no way to get fault-free frequency [Fsmu_ffs] as 2KHz because fBack is always at 100MHz and maximum PRE2 division factor is 4096.
Is that correct statement?

Or, is there any way we can divide fBack to lower than 100MHz or select any other clock for Fault Signaling Protocol feature?
Best Regards

[NeMa_4793301]

Correct: the minimum Fsmu_ffs is 24.4 KHz (with the same 2% tolerance of the 100 MHz internal oscillator).