Not found ISR routine address at IVT Table? (TC397)

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E-John
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10 replies posted First like given 25 sign-ins

Dear all,

refer to sample code "iLLD_1_0_1_12_1__TC3xx_Demos\AsclinShellInterface"

1.  Use the Linker file "Lcf_Gnuc_Tricore_Tc.lsl" under  "Aurix2G_Workspace_V1_0_1_13_0\BaseFramework_TC39B\1_ToolEnv\0_Build\1_Config\Config_Tricore_Gnuc"

2. The IVT table is set at address 0x802FE000

 

LCF_INTVEC0_START = 0x802FE000;
...

__INTTAB_CPU0 = LCF_INTVEC0_START;
...

LCF_TRAPVEC0_START = 0x80000100;
...

LCF_STARTPTR_CPU0 = 0x80000000;
...

LCF_STARTPTR_NC_CPU0 = 0xA0000000;
...

RESET = LCF_STARTPTR_NC_CPU0;

 

3. The ISR_Asc_0_rx, ISR_Asc_0_tx and ISR_Asc_0_ex are assigned to CPU0 ISR provider.

 

IFX_INTERRUPT(ISR_Asc_0_rx, 0, ISR_PRIORITY_ASC_0_RX);
IFX_INTERRUPT(ISR_Asc_0_tx, 0, ISR_PRIORITY_ASC_0_TX);
IFX_INTERRUPT(ISR_Asc_0_ex, 0, ISR_PRIORITY_ASC_0_EX);

 

4. The priority of ISR_Asc_0_rx, ISR_Asc_0_tx and ISR_Asc_0_ex are set to 4, 8 and 12

 

#define ISR_PRIORITY_ASC_0_RX 4         /**< \brief Define the ASC0 receive interrupt priority.  */
#define ISR_PRIORITY_ASC_0_TX 8         /**< \brief Define the ASC0 transmit interrupt priority.  */
#define ISR_PRIORITY_ASC_0_EX 12        /**< \brief Define the ASC0 error interrupt priority.  */

/** \} */

/**
 * \name Interrupt service provider configuration.
 * \{ */

#define ISR_PROVIDER_ASC_0    IfxSrc_Tos_cpu0         /**< \brief Define the ASC0 interrupt provider.  */

/** \} */

/**
 * \name Interrupt configuration.
 * \{ */

#define INTERRUPT_ASC_0_RX    ISR_ASSIGN(ISR_PRIORITY_ASC_0_RX, ISR_PROVIDER_ASC_0)                 /**< \brief Define the ASC0 receive interrupt priority.  */
#define INTERRUPT_ASC_0_TX    ISR_ASSIGN(ISR_PRIORITY_ASC_0_TX, ISR_PROVIDER_ASC_0)                 /**< \brief Define the ASC0 transmit interrupt priority.  */
#define INTERRUPT_ASC_0_EX    ISR_ASSIGN(ISR_PRIORITY_ASC_0_EX, ISR_PROVIDER_ASC_0)                 /**< \brief Define the ASC0 error interrupt priority.  */

 

5. Use debugger to view the CPU0 IVT Table(at address(0x802FE000), not found ISR_Asc_0_rx address(0x800022b6), ISR_Asc_0_tx address(0x800022d4) and ISR_Asc_0_ex address(0x800022f2), see attachment (IVTTAB_and_ISR_rx_tx_ex.png)

6. Is there something wrong?

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Yuva
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250 replies posted 250 sign-ins 100 solutions authored

Hello,

I believe the vector table contains the dispatcher which then calls the user defined interrupt handler. You can check in compiler user manual if you can force interrupt handler directly to vector table. 

Thanks.

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Yuva
Moderator
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250 replies posted 250 sign-ins 100 solutions authored

Hello,

I believe the vector table contains the dispatcher which then calls the user defined interrupt handler. You can check in compiler user manual if you can force interrupt handler directly to vector table. 

Thanks.

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E-John
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Use the UDE

1. click .inttab_tc0_004@184 on the left window on UDE, it will shows disassembly coe, see attach file "0-inttab_tc0_004.png"

2. The code are comiled to rsic instructions and they are placed from address 0x802F E080, which maps to IVT TAB priority = 4

3. When interrupt happens, it jump to address 0x802F E080, from here four instructions will be fetched and executed, they are

    (1). SLVCX(Save Lower Context)

    (2). Move High 16-bit address 0x8000 to cpu general purpose register A14, or "MOVH.A    a14, 0x8000"

    (3). Load Effective Address(LEA), use Base + Long Offset Addressing Mode, or "LEA    a14, [a14]0x2522"

    (4). Jump Indirect(JI) to the effective address got from step(3), or 0x8000 2522, which is the address of ISR "ISR_Asc_0_rx(void) in file "IVTTAB_and_ISR_rx_tx_ex.png"

for more details, see attach files, 01-SLVCX.png, 02-MOVH.A.png, 03-LEA.png and 04-JI.png

0-inttab_tc0_004.png

01-SLVCX.png02-MOVH.A.png03-LEA.png04-JI.png

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