Not able to write DAM memcon register

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Anusha_k_rao
Level 2
Level 2
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Hi,

I'm trying to set the ERRDIS bit in DAM's Memcon register of Infineon AURIX TC39x controller, but when the debugger executes that line, it gets stuck. I have cleared end initialization bit before I try to write.

I'm also setting ERRDIS bit of LMU's Memcon register, I'm able to write to it once I clear the end initialization bit , but the same isn't working with DAM's Memcon. Could anyone help me with this? I'm not sure what I'm missing here.

 

Thank you!

 

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1 Solution
Nambi
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50 likes received 5 likes given 100 solutions authored

Hi,

Could you check if the qualifiers "SV,E,P" for writing to the MEMCON register are met?

Best Regards.

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4 Replies
Nambi
Moderator
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50 likes received 5 likes given 100 solutions authored

Hi,

Could you check if the qualifiers "SV,E,P" for writing to the MEMCON register are met?

Best Regards.

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Anusha_k_rao
Level 2
Level 2
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Yeah that helped, Thank you.

And also when I set ERRDIS bit in DAM or LMU memcon registers, when I generate an address or data phase error the corresponding bits in memcon register doesn't set, which is as expected. But the corresponding alarms are also not setting in the SMU unit, which is not expectable. COuld you please him understand this

Thank you

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Anusha_k_rao
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And if I try generating address phase error without setting ERRDIS bit, right after the execution of line that creates error the code enters into an infinite loop but the SMU alarm will be there, but if I disable SRAM ECC errors using ERRDIS bit, SMU alarms are also not appearing. But as per the info given in user manual of LMU memcon, as shown in the image below, alarm generation should not be affected. Please help me with this

Anusha_k_rao_0-1670478848391.png

 

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Nambi
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50 likes received 5 likes given 100 solutions authored

Hi,

For both conditions, ERRDIS = "0" and ERRDIS = "1", could you check and share the following details after triggering the error condition?

1. MEMCON register.

2. SMU Alarm registers AGi.

Best Regards.

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