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User16286
Level 4
Level 4
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I'm trying to determine the QSPI TX shift register status so I can ensure all bits are sent
before deasserting the C. The context:

o I need to send data via SPI at fairly high speed (~25 Mhz).
o The L2 protocol is complex and requires manual control of CS.
o Code works correctly without DMA, but the data transfers are slow for obvious reasons.
o Switched to using DMA, but now the CS is out of sync with the data.
Specifically, the code deasserts CS before the data send is finished because
QSPI DMA tx is asynchronous.
o I tried polling QSPI_STATUS.B.PHASE but this only indicates the status of the FIFO.
The PHASE = 0 when the FIFO is empty, but the shift register may not be finished sending all bits.

So I need a method of checking the status of the Tx shift register to ensure it is empty
before deasserting CS.

Toshi
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2 Replies
cwunder
Employee
Employee
5 likes given 50 likes received 50 solutions authored
Depending on how you are using the QSPI with DMA you could configure it for short data continuous mode while using the phase transition event (PT!) to control the data flow along with the BACON allowing for a hardware controlled CS..
It also depends on how you are writing to the TXFIFO whether you are using mixed entry or the Data/BACON addresses. With continuous mode the BACON.LAST bit controls when the frame ends. Depending on how you send the data you could use the GLOBALCON1.PT1 = DNA (Data Not Available) to know when to write the BACON.LAST=1 to close the frame after the last data write.

Since the SPI always receives data you can also key on the RX interrupt to know when the tx shift has completed.
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User16286
Level 4
Level 4
First like received
cwunder wrote:
Depending on how you are using the QSPI with DMA you could configure it for short data continuous mode while using the phase transition event (PT!) to control the data flow along with the BACON allowing for a hardware controlled CS..
It also depends on how you are writing to the TXFIFO whether you are using mixed entry or the Data/BACON addresses. With continuous mode the BACON.LAST bit controls when the frame ends. Depending on how you send the data you could use the GLOBALCON1.PT1 = DNA (Data Not Available) to know when to write the BACON.LAST=1 to close the frame after the last data write.

Since the SPI always receives data you can also key on the RX interrupt to know when the tx shift has completed.


This application requires software-controlled CS.
I don't know whether the deassert CS until the received data is processed.
I think the RX interrupt idea is probably the best way to do this.
Thanks!

Toshi
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