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nsyed
Level 5
Level 5
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Can you please clarify below questions related to the peripheral clock monitoring for AURIX TC3xx device

- AURIX TC3xx monitors fPLL1 and fPLL2 loss of clock failure which is the base/source clock for QSPI & ADC.
Is there any clock monitoring on the fQSPI or fADC clocks (peripherals) ?
From user manual, I understand that there is clock monitoring on the source clock and not on individual clocks that goes to peripherals ? Is my understanding correct ?

My question here is that, how the circuitry failures after fPLLx (divider circuitry failures or any failures after divider) are detected ?
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NeMa_4793301
Level 6
Level 6
10 likes received 10 solutions authored 5 solutions authored
No, there isn't - that's why the Safety Manual contains ESM[SW]:CLOCK:PLAUSIBILITY (although that is only meant to catch errors in the Peripiheral PLL back-end K2 and K3 dividers).

There are other application-dependent ESMs to cover the case for each peripheral: ESM[SW]:GTM:TIM_CLOCK_MONITORING, ESM[SW]:EVADC:PLAUSIBILITY, etc.
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