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hamba
Level 2
Level 2
10 replies posted 25 sign-ins 5 questions asked

Hello,

I'm working on an Erika multicore project intended for execution on a TC397XE processor with TASKING v6.2r2 compiler.
At the moment, I'm focusing on the first 4 cores, and my application is designed to run in RAM, with the application loaded onto RAM via a debugger.

There is a shared code that serves as the idle task for all cores. Each core has its own dedicated RAM memory (PSPR and DSPR), but the shared code somehow is linked to the CPU5 Data Scratch-Pad SRAM (CPU5 DSPR). In the linker script, I've mapped each .text section to its respective PSPR core. I'm wondering about how the shared code is mapped to DSPR5 and how I can map it to other RAM regions.
Attached the linker script and the map file for reference (just remove the .html).

Thanks in advance.

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1 Solution
User13836
Level 6
Level 6
50 likes received 50 solutions authored 100 sign-ins

The linker by default fills the memory regions from lower to higher address ranges. Since the DSPR5 memory is starting at the lowest available address (0x10000000) the sections which are not assigned to any LSL group which does enforce a different placement will end up here. After the DSPR5 memory is used up, the linker will continue using the PSPR5 memory. Then DSPR4, PSPR4 etc.

If you would like to move the sections which do currently end up in the DSPR5 RAM to a different memory, you can define an LSL group which uses select lines to assign those sections to this group. And the group itself may be placed in a different memory.

To assign all sections starting with .text which are located in the virtual memory space (vtc) to a group and place this group somewhere in the DSPR4 memory range, you can add an entry like:

section_layout mpe:vtc:linear
{
group SHARED_CODE (run_addr = mem:mpe:dspr4) {
select "*(.text|.text*)";
}
}

to the ee_tc_tasking_flash.lsl file. 

Best regards,

Ulrich Kloidt
TASKING tools support

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2 Replies
Meet_T
Moderator
Moderator
Moderator
25 likes received 50 solutions authored 100 replies posted

Hi @User13836 , Could you please provide your help here?

Thanks,

Meet.

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User13836
Level 6
Level 6
50 likes received 50 solutions authored 100 sign-ins

The linker by default fills the memory regions from lower to higher address ranges. Since the DSPR5 memory is starting at the lowest available address (0x10000000) the sections which are not assigned to any LSL group which does enforce a different placement will end up here. After the DSPR5 memory is used up, the linker will continue using the PSPR5 memory. Then DSPR4, PSPR4 etc.

If you would like to move the sections which do currently end up in the DSPR5 RAM to a different memory, you can define an LSL group which uses select lines to assign those sections to this group. And the group itself may be placed in a different memory.

To assign all sections starting with .text which are located in the virtual memory space (vtc) to a group and place this group somewhere in the DSPR4 memory range, you can add an entry like:

section_layout mpe:vtc:linear
{
group SHARED_CODE (run_addr = mem:mpe:dspr4) {
select "*(.text|.text*)";
}
}

to the ee_tc_tasking_flash.lsl file. 

Best regards,

Ulrich Kloidt
TASKING tools support