MTU_FAULTSTS.OPERR[1] is set after reset

[Jamber]

Hi all, 

In safetymanual, ESM[SW]:SYS:MCU_FW_CHECK give the value of MTU_FAULTSTS after reset, and software should check it.

The value for SSH0(CPU0_DMEM) is 0x0B in my board, but the given value is 0x09. OPERR[1] is set additionally in my board, It's means " Auto-data-init or Partial erase (caches) was triggered, resulting in overwriting of SRAM", but I don't understand, please tell me the reason and how to deal with it, thank you.

Best Regards

[Jamber]

The result for other modules:

			WarmPORST_Val_Expected			WarmPORST_Val_Real
SSH_ID	Module	Auto-Init	ECCD	FAULTSTS	ERRINFO[0]	ECCD	FAULTSTS	ERRINFO[0]
0	CPU0_DMEM	Y	5	9	0	5	11	0
1	CPU0_DTAG	N	5	1	0	5	11	0
2	CPU0_PMEM	Y	5	9	0	5	11	0
3	CPU0_PTAG	N	5	1	0	5	11	0
4	CPU0_DLMU_STBY	Y	5	9	0	5	9	0
5	CPU1_DMEM	Y	5	9	0	5	11	0
6	CPU1_DTAG	N	5	1	0	5	11	0
7	CPU1_PMEM	Y	5	9	0	5	11	0
8	CPU1_PTAG	N	5	1	0	5	11	0
9	CPU1_DLMU_STBY	Y	5	9	0	5	9	0
10	CPU2_DMEM	Y	5	9	0	5	11	0
11	CPU2_DTAG	N	5	1	0	5	11	0
12	CPU2_PMEM	Y	5	9	0	5	11	0
13	CPU2_PTAG	N	5	1	0	5	11	0
14	CPU2_DLMU	Y	5	9	0	5	11	0
34	CPU0_DMEM1	N	5	1	0	5	11	0
35	CPU1_DMEM1	N	5	1	0	5	9	0
38	DAM0	N	5	1	0	5	1	0
41	SADMA	N	5	1	0	5	1	0
42	MINI_MCDS	N	5	1	0	5	1	0
53	GTM_FIFO	N	5	1	0	5	1	0
55	GTM_MCS0FAST	N	5	1	0	5	1	0
57	GTM_MCS1FAST	N	5	1	0	5	1	0
58	GTM_DPLL1A	N	5	1	0	5	1	0
59	GTM_DPLL1BC	N	5	1	0	5	1	0
60	GTM_DPLL2	N	5	1	0	5	1	0
62	M_CAN10	N	5	1	0	5	1	0
63	M_CAN20	N	5	1	0	5	1	0
65	PSI5	N	5	1	0	5	1	0
66	ERAY_OBF0	N	5	1	0	5	1	0
68	ERAY_TBF_IBF0	N	5	1	0	5	1	0
70	ERAY_MBF0	N	5	1	0	5	1	0
77	SCR_XRAM	N	5	1	0	0	9	0
78	SCR_RAMINT	N	5	1	0	0	9	0
82	GIGETH_RX_RAM	N	5	1	0	5	1	0
83	GIGETH_TX_RAM	N	5	1	0	5	1	0

[Jamber]

Hi, IFX

I need help! Thank you 

Best regards

[Jamber]

Hi,

Help me pleeeeeeeeeeeeeeeeeeeeease!

Best Regards

[Nambi · Accepted solution]

Hi,

Please contact the local sales/ FAE team since the safety topic needs an NDA and cannot be discussed in the public forum.

Best Regards.