AURIX™ Forum Discussions

[#1]

Hi,

In the MPU implementation, DPR0_L & DPR0_U are 32 bit aligned registers. For DPR0_L, the key word “align in the linker will ensure the alignment, however for DPR0_U this is not guaranteed. If the DPR0_U is not 32-bit aligned, while writing into the register, the address is truncated to the lesser nearest 32-bit address. Thus how can an application ensure that the MPU registers are not loaded with the truncated ranges, because at runtime, if a variable that exist into the truncated region is accessed, a fault will be encountered.

E.g. For a memory section in range 0x70000028 and 0x70000034 for this the DPR0_U will be truncated to 0x70000030, thus any access to variables in range 0x70000030 and 0x70000034, will cause a fault, which is undesirable.

I am reading the memory section in linker as -
"START_APP1_BLOCK0" := addressof(group:APP1_BLOCK0);
"END_APP1_BLOCK0" := addressof(group:APP1_BLOCK0) + sizeof(group:APP1_BLOCK0);


Platform used - Tasking 4.2r2

[µC_Wrangler]

amitoza88 wrote:
In the MPU implementation, DPR0_L & DPR0_U are 32 bit aligned registers. For DPR0_L, the key word “align in the linker will ensure the alignment, however for DPR0_U this is not guaranteed. If the DPR0_U is not 32-bit aligned, while writing into the register, the address is truncated to the lesser nearest 32-bit address. Thus how can an application ensure that the MPU registers are not loaded with the truncated ranges, because at runtime, if a variable that exist into the truncated region is accessed, a fault will be encountered.

E.g. For a memory section in range 0x70000028 and 0x70000034 for this the DPR0_U will be truncated to 0x70000030, thus any access to variables in range 0x70000030 and 0x70000034, will cause a fault, which is undesirable.

I am reading the memory section in linker as -
"START_APP1_BLOCK0" := addressof(group:APP1_BLOCK0);
"END_APP1_BLOCK0" := addressof(group:APP1_BLOCK0) + sizeof(group:APP1_BLOCK0);


Platform used - Tasking 4.2r2

The protection registers require 64-bit (8 byte) alignment, since the lower 3 bits are always 0.

I'm not sure how you're defining the APP1_BLOCK0 group, but if you can make it 8 bytes bigger, and make sure subsequent sections are also aligned to an 8-byte boundary, then the alignment of DPR0_U will always be okay. It might be as easy as this:

"END_APP1_BLOCK0" := addressof(group:APP1_BLOCK0) + sizeof(group:APP1_BLOCK0) + 8;

[#3]

Hi Neal,

Thanks for the clarification. However do we have any application note or this documented in any Infineon documents? I will need to refer that in my design document.

If you are aware about any such reference, kindly share.