MCi_ECCS (i=0-95): How to identify correct register for SRAM

[Dev_07]

I am using TC387 target. 

1. I need to access MCi_ECCS [i = 0-95] for CPU0 DSRAM. I want to know which register index I need to select to access CPU0 DSRAM(I am looking for i value for CPU0 DSRAM). 

I was looking for where I can find this mapping in the user manual, I could not get much out of it. (On-Chip System Connectivity chapter in the usermanual. )

Can some one pls help me to identify correct register index. 

2. I am trying to generate ECC for the testing purpose, in the normal software running state.

     I am trying to access ECCMAP bits to achieve this.

pls let me know if we have an easy wat to generate ECC error [for testing purpose] for SRAM. 

[DownyK]

Hello Dev_07

1. you can find SSH instances ID in TC38x_appx_um_v2.0.pdf. 

2. I think setting the test you want is very difficult... 

But, why did you want to make this test? is its purpose to check SMU alarm for ECC? 

As I know, Infineon does not recommend this type of test. 

in my case, I and my team had reviewed only, not tested SMU alarm config. 

[Dev_07]

Hi,

Thank you for the reply. 

I am trying to write test software for ECC detection/correction. 

So i am trying to generate ECC error for SRAM & check if a particular alarm is reported. This is ECC error injection for testing purpose. 

From above table[in your post], can I conclude that for CPU0 DSRAM I need to use MC0 ? 

thanks.

[DownyK]

Hi Dev_07

um.. what is DSRAM? Do you mean DMEM? 

in the SSH list, There is no DSRAM. 

[Dev_07 · Accepted solution]

Hi,

DS RAM is CPU data scram pad RAM. As you mentioned  It should be DMEM. 

thanks.