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jackp0t
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Hi everyone,

I have a question about MBIST.

If I directly call the IFX_CFG_SSW_CALLOUT_MBIST() function, there are no issues. However, if I perform a clear operation on CPU0DSPR before calling this function, it causes the program runs out of control while running MBIST.

Can anyone tell why and how to resolve it.

Best Regards,

Jackp0t

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1 Solution
Jeremy_Z
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250 sign-ins 100 likes received 750 replies posted

Hi @jackp0t 
Thanks for your reply and code sharing.
After checking, during the TC3xx start-up process, it definitely will call IFX_SSW_INIT_CONTEXT function the in Phase 3.
And in the function, it will set the A10 (SP) register to point to the dsram, so your code will disrupt the stack area which locates in the dsram, then cause program crash.

#define IFX_SSW_INIT_CONTEXT()                                                   \
    {                                                                            \
        /* Load user stack pointer */                                            \
        Ifx_Ssw_setAddressReg(a10, __USTACK(0));                                 \
        Ifx_Ssw_DSYNC();                                                         \
                                                                                 \
        /*Initialize the context save area for CPU0. Function Calls Possible */  \
        /* Setup the context save area linked list */                            \
        Ifx_Ssw_initCSA((unsigned int *)__CSA(0), (unsigned int *)__CSA_END(0)); \
        /* Clears any instruction buffer */                                      \
        Ifx_Ssw_ISYNC();                                                         \
    }


Hope it helps.
BR,
Jeremy

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5 Replies
Jeremy_Z
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250 sign-ins 100 likes received 750 replies posted

Hi @jackp0t 
I think I need more information about the phenomenon, so I was wondering if you can illustrate the steps of replicating the issue in detail.
Looking forward to your reply.
BR,
Jeremy

 

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Hi Jeremy,

Thanks for your reply. Here are the details of the issue I encountered:
1. For MBIST, I followed the approach in Infineon TC3xx iLLD and enabled the IFX_CFG_SSW_ENABLE_MBIST API during the Startup Software phase. The program can execute MBIST properly.
2. Before executing MBIST, I manually write all the CPU0_DSPR SRAM to 0, and then execute MBIST. However, I observed that the program crashes as soon as it enters the MBIST. But when I manually write all the CPU0_PSPR SRAM to 0, MBIST can execute without any issues.

Looking forward to your reply.

Best Regards,

Jackp0t

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Jeremy_Z
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250 sign-ins 100 likes received 750 replies posted

Hi @jackp0t 
Thanks for your reply.
Can you share the code for writing all the CPU0_DSPR SRAM to 0?
Next, I'm a bit confused with the below sentence, can you explain it again?
But when I manually write all the CPU0_PSPR SRAM to 0, MBIST can execute without any issues.
BR,
Jeremy

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Hi Jeremy,

Here's my snippet:

static void __StartUpSoftware_Phase4(void)
{
    /* This is for ADAS chip, where clock is provided by MMIC chip. This has to be
     * implemented according the board.
     */
    IFX_CFG_SSW_CALLOUT_MMIC_CHECK();

    {
        /* Update safety and cpu watchdog reload value*/
        unsigned short cpuWdtPassword = Ifx_Ssw_getCpuWatchdogPasswordInline(&MODULE_SCU.WDTCPU[0]);
        unsigned short safetyWdtPassword = Ifx_Ssw_getSafetyWatchdogPasswordInline();

        /* servicing watchdog timers */
        Ifx_Ssw_serviceCpuWatchdog(&MODULE_SCU.WDTCPU[0], cpuWdtPassword);
        Ifx_Ssw_serviceSafetyWatchdog(safetyWdtPassword);
    }

    /* Initialize the clock system */
    IFX_CFG_SSW_CALLOUT_PLL_INIT();
    sram_clear();
    /* MBIST Tests and evaluation */
    IFX_CFG_SSW_CALLOUT_MBIST();

    Ifx_Ssw_jumpToFunction(__StartUpSoftware_Phase5);
}
void sram_clear(void)
{
    /*write CPU0_DSPR SRAM to 0*/
    uint32 SRAM_BASE_ADDRESS = 0x70000000;
    uint32 SRAM_SIZE = 245760;
    uint32* sram_ptr = (uint32*)SRAM_BASE_ADDRESS;
    uint32 sram_length = SRAM_SIZE / sizeof(uint32);

    for (uint32 i = 0; i < sram_length; i++)
    {
        *sram_ptr++ = 0;
    }
}
As you know, if I write all the CPU0_DSPR SRAM to 0, the program will crash; so I choose to write all the CPU0_PSPR SRAM to 0, the MBIST will pass and the program runs properly.
And here's my code:
void sram_clear(void)
{
    /*write CPU0_PSPR SRAM to 0*/
    uint32 SRAM_BASE_ADDRESS = 0x70100000;
    uint32 SRAM_SIZE = 65536;
    uint32* sram_ptr = (uint32*)SRAM_BASE_ADDRESS;
    uint32 sram_length = SRAM_SIZE / sizeof(uint32);

    for (uint32 i = 0; i < sram_length; i++)
    {
        *sram_ptr++ = 0;
    }
}
BR,
Jackp0t
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Jeremy_Z
Moderator
Moderator
Moderator
250 sign-ins 100 likes received 750 replies posted

Hi @jackp0t 
Thanks for your reply and code sharing.
After checking, during the TC3xx start-up process, it definitely will call IFX_SSW_INIT_CONTEXT function the in Phase 3.
And in the function, it will set the A10 (SP) register to point to the dsram, so your code will disrupt the stack area which locates in the dsram, then cause program crash.

#define IFX_SSW_INIT_CONTEXT()                                                   \
    {                                                                            \
        /* Load user stack pointer */                                            \
        Ifx_Ssw_setAddressReg(a10, __USTACK(0));                                 \
        Ifx_Ssw_DSYNC();                                                         \
                                                                                 \
        /*Initialize the context save area for CPU0. Function Calls Possible */  \
        /* Setup the context save area linked list */                            \
        Ifx_Ssw_initCSA((unsigned int *)__CSA(0), (unsigned int *)__CSA_END(0)); \
        /* Clears any instruction buffer */                                      \
        Ifx_Ssw_ISYNC();                                                         \
    }


Hope it helps.
BR,
Jeremy