LBIST execution TE and TP

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
Kumaresh
Level 3
Level 3
10 questions asked 10 replies posted First solution authored

Hi,

Is there any difference in LBIST execution between TC37x TE and TP ?

Thanks!

0 Likes
1 Solution
Di_W
Moderator
Moderator
Moderator
500 solutions authored 1000 replies posted 250 solutions authored

dw_0-1649488603314.png

 

From the AURIXTC3XX_um_part1_v2.0.pdf , 0-95 is seperated by set DONE bitfiled.

 

View solution in original post

0 Likes
11 Replies
Di_W
Moderator
Moderator
Moderator
500 solutions authored 1000 replies posted 250 solutions authored

Hi,

I have checked  TC37XED_ts_appx_V2.5.1.pdf , TC37X_ts_appx_V2.5.1.pdf and no found difference.

About register configurations, please refer to TC37x_appx_um_v2.0.pdf and TC37xEXT_appx_um_v2.0.pdf, the last one is for TE device.

dw

 

 

0 Likes
Kumaresh
Level 3
Level 3
10 questions asked 10 replies posted First solution authored

Hi,

Thanks. I do have have 2 more questions as below:

1. Will there be any problem if we don't initialize SRAM content before we write something to it after LBIST execution (SCU_TC.H022 Effect of LBIST execution on SRAMs - Additional information  TC37x_AA_Errata_Sheet_v1_4)

2. Do the above errate applicable for external memory as well i.e for TE chip ?

Note that we are excuting LBIST from our application SW  and not in SSW.

0 Likes
Di_W
Moderator
Moderator
Moderator
500 solutions authored 1000 replies posted 250 solutions authored

dw_0-1649228604949.png

From above picture, SRAMs include EMEM.  For EMEM initialization, below is from TC37xEXT_appx_um_v2.0.pdf - Section 13.3 SRAMs with Address ECC:
For these SRAMs/SSHs, initializing the SRAM with ECC correct data using MCONTROL.DINIT is not supported. The SRAMs can be still completely initialized via the MCONTROL.SRAM_CLR bit (Refer platform specification chapter on Filling a Memory with Defined Contents).

If not to initialize the EMEM, the result will be unknown as below - TC37xEXT_AB_Errata_Sheet_v1_9_10297AERRA.pdf:

Note: SRAM redundancy registers are part of the scan chain and hence corrupted by LBIST. Therefore, SRAMs contents are not reliable after LBIST and shall be initialized after LBIST, prior to usage.
DLMU SRAM with standby capability can be used instead to store information such as the LBIST execution count.

0 Likes
Kumaresh
Level 3
Level 3
10 questions asked 10 replies posted First solution authored

Thanks for the detailed info. I tried to clear SRAM and encounter some problem so need info on below questions so it will help us in debugging

(1) How to check whether SRAM is initialized (particularly EMEM) ?

(2) I used  function IfxMtu_clearSramStart from IfxMtu to clear SRAM content (to initialize SRAM to zero) but it generates bus error. Before calling this function I made sure that MTU_CLC is 0. I referred to Ch 13.3.5.1.5 and this func satisfied all the precondition. Am I missing something?

0 Likes
Di_W
Moderator
Moderator
Moderator
500 solutions authored 1000 replies posted 250 solutions authored

Hi 

In Libraries\iLLD\TC37A\Tricore\Mtu\Std\IfxMtu.h, there is a short description, you can refer. Otherwise, I found an enumeration type IfxMtu_MbistSel. Have you used it?

0 Likes
Kumaresh
Level 3
Level 3
10 questions asked 10 replies posted First solution authored

Hi,

I am trying to enable MTU so that it can initialize SRAM. May I know how to verify SRAM is initialized? Is there any specific condition need to take on performing MTU for EMEM.

0 Likes
Di_W
Moderator
Moderator
Moderator
500 solutions authored 1000 replies posted 250 solutions authored

You could know the SRAM init completed by  MSTATUS.DONE, but the hardware operations is not externnaly verified unless youself test by software which is very slowly. Details are described in 13 Memory Test Unit (MTU) AURIXTC3XX_um_part1_v2.0.pdf

0 Likes
Kumaresh
Level 3
Level 3
10 questions asked 10 replies posted First solution authored

The default value (from application reset) of MSTATUS.DONE is 0xFFFFFFFF so checking this parameter will be alone sufficent to conclude that SRAM / any memory is initialized

0 Likes
Di_W
Moderator
Moderator
Moderator
500 solutions authored 1000 replies posted 250 solutions authored

If you use the Application start-up software, the MBIST will run init SRAM also.

dw_0-1649415442983.png

 

0 Likes
Kumaresh
Level 3
Level 3
10 questions asked 10 replies posted First solution authored

Hi, We are not running MBIST from SSW. We call it  from our own _START where we trigger LBIST first and later calling the MBIST.

In this MBIST test I am not performing any test in EMEM. ( I am able to confirm that in MEMTESTi, EMEM is not enabled only memory region which we intendent to test MBIST alone enabled) But still I see MSTATUS is DONE for EMEM.

My question is does triggering MBIST will initialize all the memory region particularly (SRAM).

The background for this question is if I run only LBIST and when application tries to write something into EMEM it raises an exception. And this issue is not reproduced if LBIST is not executed

0 Likes
Di_W
Moderator
Moderator
Moderator
500 solutions authored 1000 replies posted 250 solutions authored

dw_0-1649488603314.png

 

From the AURIXTC3XX_um_part1_v2.0.pdf , 0-95 is seperated by set DONE bitfiled.

 

0 Likes