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Jonson
Level 3
Level 3
50 sign-ins 10 questions asked 25 replies posted

HI experts:
When I debug the code for sent communication in the ILLD library, I find that the code loops in these two places, but does not read the sent data. Please help to analyze the reason?

微信图片_20240407202248.png微信图片_20240407202258.png

 

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4 Replies
NXTY_Mori
Level 5
Level 5
Distributor - NEXTY (Japan)
50 likes received 25 likes received 50 replies posted

Hello @Jonson-san,

- FRI bit is set after a Synchronization / Calibration pulse was received that deviates more than +/- 25% from the nominal value.
- NVI bit is set after a too long or too short nibble pulse has been received.

Please check the User Manual and make settings within the appropriate range.
https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Part2-UserManual-v02_00-EN.pdf?fileId=5546d462712...


Best Regards,
Mori

Mori,

Thank you for your patient reply!I would also like to ask how this 0x7 in Infineon's example "iLLD_TC375_ADS_TLE5014_Interface_SENT_Simple" came about.

微信图片_20240410155009.png

Jonson
Level 3
Level 3
50 sign-ins 10 questions asked 25 replies posted

0x7=0b111, whether the corresponding registers RBI, RDI and RSI are triggered respectively.

NXTY_Mori
Level 5
Level 5
Distributor - NEXTY (Japan)
50 likes received 25 likes received 50 replies posted

Hello @Jonson-san,

I couldn't understand the intent of the question.
0x7u on the 207th line is the RBI bit, RDI bit, and RSI bit of the INTSTAT register.
Please check the User Manual for a description of each bitfield in the INTSTAT register.

If the content of your question is an explanation about the code, I think it will be as follows.
- IfxSent_Sent_getAndClearInterruptStatus function gets the setting value of the INTSTAT register of the SENT channel set as an argument.
- If the RBI bit, RDI bit, and RSI bit are not all set in the acquired INTSTAT register setting value, execute the processing of the IfxSent_Sent_readChannelSerialDataFrame function.

Does this answer your question?

Best Regards,
Mori.