Is Cache Coherency covered in Hardware?

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User17612
Level 4
Level 4
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Hi all,

Does AURIX have a cache coherency mechanism in hardware that ensures cache coherency between different core caches?

Thank you and best regards
Lucas


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User18151
Level 3
Level 3
First like received First solution authored
Hi Lucas,

No, this is not covered automatically in hardware. However each memory section can be accessed as well using an uncached address (therefore same physical memory is adressed but cache is bypassed).
Also there are special instructions to ensure a proper cache write back: CACHEI and CACHEA instructions.

Please refer to the TriCore Architecture Manual for a detailed description.

Best regards
Christine
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