Internal read-modify write

[Anusha_k_rao]

Hi,

What is mean by read-modify write operation? I don't understand how does this actually works. And also in LMU module MEMCON.RMWERR has to be tested, and the User manual says it is set when an uncorrected ECC error is reported by the RAM on the read phase of an internal RMW operation. Please do enlighten me on how can this error be generated and tested.

[Di_W]

Hi,

Read modify and write is an atomic operation.  You can refer to here.

I will supplement here for error injection method if get any.

dw

[Anusha_k_rao]

I understood what exactly is read modify write error but I'm not sure of how to generate an error during that operation.

And as per user manual, SCTRL register bit 1 is supposed to generate ECC error during the next read access,

But I don't see any error being injected in MEMCON register when I read the LMU ram. When bit 0 of SCTRL is set and when I try to write to LMU RAM I see error being generated. But this is not working when I try to do the same while I read the LMU RAM with SCTRL bit 1 set . Do I miss something here? Please let me know how to inject an error during RAM read.

[Anusha_k_rao]

Similarly, in CPU_SEGEN register 

When ADDFLIP bit[9:8] is set to 10 it is supposed to inject an error when LMU RAM is read but even here I don't see generation of any errors in MEMCON. But I could test both Data Master Address phase and data phase errors, I could see the error occurence in MEMCOn register,  but only for Data slave read data I'm not able to see any error generating

[Di_W]

Maybe below code samples helpful for you

To trigger the alarm ALM11[3] by injecting a write phase error with SEGEN and the writing to an XBAR register:

__mtcr (CPU_SEGEN, 0x80000101);
 MODULE_DOM0.SCICTRL[0].PECON.U = 0x0;

ALM0[23]: by doing the following

__mtcr (CPU_SEGEN, 0x80000203); //Inject read slave data error
dummy = *(volatile uint32 *) 0x70100000; //read from dspr0

For ALM11[8], so far impossible to inject a DAM ECC error.

And, please note that basically AE bit is cleared by the first read access into the CPU - it could be a debugger or any other CPU.

[Anusha_k_rao]

---

@Di_W wrote:

Maybe below code samples helpful for you

To trigger the alarm ALM11[3] by injecting a write phase error with SEGEN and the writing to an XBAR register:

__mtcr (CPU_SEGEN, 0x80000101);
 MODULE_DOM0.SCICTRL[0].PECON.U = 0x0;

ALM0[23]: by doing the following

__mtcr (CPU_SEGEN, 0x80000203); //Inject read slave data error
dummy = *(volatile uint32 *) 0x70100000; //read from dspr0

For ALM11[8], so far impossible to inject a DAM ECC error.

And, please note that basically AE bit is cleared by the first read access into the CPU - it could be a debugger or any other CPU.

---

This is how exactly I'm trying to write and read into LMU RAM, as you have mentioned AE bit is cleared before I execute LMU read statement. But even if AE bit is vanished sooner than I read, atleast error should have been generated in MEMCON when the LMU RAM is first read is it? I don't see any bit set in MEMCON

[Di_W]

/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
 *
 *  Alarm 11[0] LMU EDC Read Phase Error Injection
 *
 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */

void LMU_EDC_Read_Phase_Error_Injection(void){
	IfxScuWdt_clearCpuEndinit(IfxScuWdt_getCpuWatchdogPassword());
	Ifx_CPU_SEGEN SEGEN;
	SEGEN.U=0;
	SEGEN.B.ADTYPE=0;//Master Address Error
	SEGEN.B.ADFLIP=1;//Flip=ON
	SEGEN.B.AE=1;//Error Enabled
	__mtcr(CPU_SEGEN, SEGEN.U);
	IfxScuWdt_setCpuEndinit(IfxScuWdt_getCpuWatchdogPassword());
	LMU0_CLC.U;
}


/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
 *
 *  Alarm 11[1] LMU EDC Write Phase Error Injection
 *
 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */

void LMU_EDC_Write_Phase_Error_Injection(void){
	IfxScuWdt_clearCpuEndinit(IfxScuWdt_getCpuWatchdogPassword());
	Ifx_CPU_SEGEN SEGEN;
	SEGEN.U=0;
	SEGEN.B.ADTYPE=1;
	SEGEN.B.ADFLIP=1;
	SEGEN.B.AE=1;
	__mtcr(CPU_SEGEN, SEGEN.U);
	LMU0_CLC.U=0x0;
	IfxScuWdt_setCpuEndinit(IfxScuWdt_getCpuWatchdogPassword());
}

For ALM11[0] and ALM11[1] error injection, above examples are for your reference.

For ALM7[14] and[16], below example is for your reference.

/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
 *
 *  Alarm 7[16] LMU EDC Error Injection
 *
 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */

void LMU_Read_ECC_Error_Injection(void){
    IfxScuWdt_clearSafetyEndinit(IfxScuWdt_getSafetyWatchdogPassword());
    LMU0_SCTRL.B.GEC=1;
    IfxScuWdt_setSafetyEndinit(IfxScuWdt_getSafetyWatchdogPassword());
	read_with_DMA((volatile uint32*)0x90040000,(volatile uint32*)0x90040010,1);
}

/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
 *
 *  Alarm 7[14] LMU ECC Error Injection
 *
 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */

void read_with_DMA(uint32* source,uint32* destination,int num){

	DMA_SADR005.U=(uint32)source;
	DMA_DADR005.U=(uint32)destination;
	DMA_CHCFGR005.U=(0x2<<21)|(0x1<<19)|num; //32bits, no request needed for each transfer
	DMA_ADICR005.U=(1<<3)|(1<<7)|(0<<16); //Shadow Control Move Operation
	DMA_TSR005.U|=(1<<17); //Hardware request disable
	DMA_CHCSR005.U|=(1<<31); //Start Transaction
	__dsync();
	for(volatile int i=0;i<10000;i++){
		__nop();
	}
}

void read_with_DMA_256bit(uint32* source,uint32* destination,int num){

	DMA_SADR005.U=(uint32)source;
	DMA_DADR005.U=(uint32)destination;
	DMA_CHCFGR005.U=(0x5<<21)|(0x1<<19)|num; //256bits, no request needed for each transfer
	DMA_ADICR005.U=(1<<3)|(1<<7)|(0<<16); //Shadow Control Move Operation
	DMA_TSR005.U|=(1<<17); //Hardware request disable
	DMA_CHCSR005.U|=(1<<31); //Start Transaction
	__dsync();
	for(volatile int i=0;i<10000;i++){
		__nop();
	}
}



void LMU_ECC_Error_Injection(void){
	IfxScuWdt_clearSafetyEndinit(IfxScuWdt_getSafetyWatchdogPassword());
	((Ifx_MTU*)0xF0060000u)->MC[IfxMtu_MbistSel_lmu0].ECCS.B.SFLE=1;
	IfxScuWdt_setSafetyEndinit(IfxScuWdt_getSafetyWatchdogPassword());
	volatile uint32 temp_hoge=0;
	read_with_DMA((uint32*)0x90040000,&temp_hoge,1);
}

[Anusha_k_rao]

Thank you for the references. I would like to have some example with below  value that's for Data slave read

SEGEN.B.ADTYPE=2;

 With ADTYPE being 1 and zero, I have got the results successfully already. And code snippets for read-modify-write would be very helpful

[Di_W]

Please refer to below for ADTYPE=2

/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
 *
 *  Alarm 0 [23] SRI end-to-end Inject Fault (Data)
 *
 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */

void SRID_End_to_End_EDC_Inject_Fault(){
	volatile uint32 temp_read;
	IfxScuWdt_clearCpuEndinit(IfxScuWdt_getCpuWatchdogPassword());
	Ifx_CPU_SEGEN SEGEN;
	SEGEN.U=0;
	SEGEN.B.ADTYPE=2;
	SEGEN.B.ADFLIP=1;
	SEGEN.B.AE=1;
	__mtcr(CPU_SEGEN, SEGEN.U);
	IfxScuWdt_setCpuEndinit(IfxScuWdt_getCpuWatchdogPassword());
	temp_read=*(volatile uint32*)0x70100000;
	/*Bus error occurs and will jump to trap handler*/
}

[Anusha_k_rao]

Could you please help me get the read-modify write error steps? I'm not able to get them

[Anusha_k_rao]

Hi,

In LMU register, 

In the above register if GEC bit is set I should see internal ECC error when I try to read from the LMU SRAM, but I don't see it happening. But similarly when GED bit is set I should see internal ECC error on write access to LMU, that is working. But the write to GEC bit doesn't works as accepted, do I miss something here?

[Di_W]

The RMW error can only be triggered by iRMW on LMU SRI slave side, not on CPU slave side. To trigger RMW error you need to inject ECC errors into the SRAM and perform a sub-64bit write operation. Injecting ECC errors might be possible by disabling SRAM initialization at startup.