Announcements

Help us improve the Power & Sensing Selection Guide. Share feedback

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
User19083
Level 1
Level 1
Hello,

New to AURIX TC3xx, going through the documentation.

I see the DAM module, an apparently new 32-64kb SRAM available at SRI, additional to LMU - have doubt on its intended usage. Posting here in case somebody has some remark on that.

It pretty much resembles LMU, according to what I get from documentation, with the differences:

-DAM is not ASIL-x compliant

Then, provided that, for example in TC397 DAM is actually smaller than LMU (64kb vs 256kb), and actually has more latency (according to table 74 of latencies), I'm wondering: What is the intended usage of the DAM? Wouldn't LMU be more suitable in all cases? (bigger, faster, and ASIL-D).

Also, I wonder in which sense it's non-ASIL-x: Functionally, from doc, is very similar to LMU, including ECC, etc. The non-ASIL-x qualification comes from the way it's been implemented/silicon?

Greetings,
0 Likes
6 Replies
NeMa_4793301
Level 6
Level 6
10 likes received 10 solutions authored 5 solutions authored
The DAM is the memory for the Advanced Modeling Unit (AMU), a secretive hardware accelerator described in this paper:
https://www.sae.org/publications/technical-papers/content/2020-01-1366/

If you're not using the AMU, then it's just a bonus blob of RAM your application can use. Generally, the LMU is more suitable for safety-relevant data.
0 Likes
User19083
Level 1
Level 1
Hello,

Thanks for reply and link.

Now clearer - didn't come accross that module/unit.

Do you have any idea on why DAM may not be so suitable for safety? Still a bit puzzled about that as, functionally, LMU & DAM look so similar.

Thanks,
0 Likes
NeMa_4793301
Level 6
Level 6
10 likes received 10 solutions authored 5 solutions authored
The AMU+DAM are a block of IP that are QM, and thus lack the additional bells and whistles such as ECC monitor logic.
0 Likes
User20365
Level 1
Level 1
Hello guys,

Also new to Infineon AURIX.
I saw this post and I'm also interested in the reason why DAM is not ASIL x-comliant.
In the AURIX_TC3xx_UserManual at P. 575 and P. 590, it mentions that the data in DAM and also LMU is protected by ECC.
There are also memory protection and register protection.
The mechanisms of both do look similar.

Are there other factors take a part?

Thank you
0 Likes
Darren_Galpin
Employee
Employee
First solution authored First like received
Yes - things such as is the entire data path from the RAM to the system interconnect protected. Although the SRAM may indicate that there was an error on the stored data, this does not mean that the data is then protected until it reaches the bus (where it would again be protected).
0 Likes
User20365
Level 1
Level 1
Hello Darren,

I see. Thank you for your reply!

Best regards,
Ruby
0 Likes