Infineon Aurix TC39X LMU test

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Anusha_k_rao
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Hi,

 

I'm trying to test LMU module of Infineon AURIX TC39X, but I don't seem to find registers that enable write data or address to LMU, there are no clear steps to test the module either. If I check in forums or web all I get is testing memories via MTU module. There are registers like MEMCON, STRL which helps to generate error or monitor error during read or write access to SRAM. But there is no clear information on how exactly to read or write to LMU SRAM. Please help me with some document to test LMU or some code examples.

 

I have also attached snapshot of the module that I'm trying to test, for the clarity.

 

Hope to get the resolution soon!

 

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Di_W
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        /* Set PSW.IO to 2 (supervisor mode). This is needed for certain operations
         * performed below. */
        __mtcr(PSW, (int) (((unsigned int) __mfcr(PSW) & 0xfffff3ffU) | 0x800U));

Please try to use supervisor mode

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Di_W
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Anusha_k_rao_0-1664449901321.png

But I have to test the ECC errors listed in the image above, within LMU memory. But I don't seem to find the exact steps to test these errors of LMU. Whatever was suggested in the above reply is just storing  variable into the memory and trying to read back. But here there are 3 separate LMU modules LMU0, LMU1 and LMU2

Anusha_k_rao_1-1664450090659.png

each of which has separate LMU registers CLC ,MODID ,ACCEN0 ,ACCEN1 ,MEMCON ,RGNLAx ,RGNUAx ,RGNACCENWAx ,RGNACCENWBx ,RGNACCENRAx ,RGNACCENRBx[Referring to section 7.3] using which I have to generate ECC errors. 

Help me with the steps to test the above once, how exactly those errors could be generated and tested

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Di_W
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Please refer to below description:

When error injection is being performed for LMU SRI Write Data Phase Error (ALM11[1]), the LMU ECC Error (ALM[7[14]) is also occurring.

The error injection method followed for LMU SRI Write Data Phase Error is 

 Set CPU_SEGEN.ADFLIP = 1, CPU_SEGEN.ADTYPE = 1(Data Phase), and CPU_SEGEN.AE = 1 and then write to LMU RAM.

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Okay Thank you!.. But each time I try writing to either CPU->SEGEN or LMU->SCTRL I get into exceptions. Does safetyendinit or endinit functions has something to play here? Or should I add an enable bit to any of other registers ?

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MoD
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CPU.SEGEN is CPUx endinit protected and LMU.SCTRL is safety endinit protected. Before you write to this registers you must make sure the corresponding endinit bit is cleared and set otherwise after the access.

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Di_W
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https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Part1-UserManual-v02_00-EN.pdf?fileId=5546d462712...

Please refer to above user manul for this chapter: 1.1.6 Register Access Modes

dw_0-1664526644936.png

 

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By default safety endinit [Safety WDT Control Register 0]and endinit[CPUy WDT Control Register 0 , endinit bit is 0 by default for CPU0] registers are in a state for CPU0, that they should allow modify CPU_SEGEN and LMU_SCTRL without any modification for the registers. But seems like CPU_SEGEN and LMU_SCTRL has to be read/write in supervisor mode, how do we get into supervisor mode on Infineon AURIX?

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The document says after reset value for CPUy WDT Control Register
0  for CPU 0   and Safety WDT Control Register0 is  FFFC 000E but when it is read over Infineo AURIX eval board the value is  FFFC 000F which is contradictory. In this case I'll have to manually clear Safety endinit and Endinit.

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After clearing safety endinit I'm able to write to LMU_SCTRL but even after clearing endinit not able to write to CPU_SEGEN, do I miss anything here? Should I enable any other registers here?

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Hi,

I'm trying to generate SRI address and data phase errors inorder to test LMU SRAM module.

I have set the ENDINIT bit of both ENDINIT Global Control Register 0 and CPU0 WDT control register and trying to access CPU0.SEGEN [ CPU0 = 0xF8800000u]. But both read and write access to this register is not possible. If I see the register addressing mode section, it seems all the conditions are satisfied but even then I'm not able to modify the bits of this register. Please do enlighten me on this part, on how to access the register.

Anusha_k_rao_0-1664863922287.png

 

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Di_W
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Hi,

As ENDINIT has a limited time window, so please make sure to modify the target register in the window, or you can refer to ENDINIT function in the iLLD.

 * {                                                      \
 *     uint16 passwd = IfxScuWdt_getCpuWatchdogPassword();\
 *     IfxScuWdt_clearCpuEndinit(passwd);                 \
 *     MODULE_ASCLIN.CLC.B.DISR = 1;                      \
 *          MODULE_EVADC.CLC.B.DISR = 1;                        \
 *          MODULE_EDSADC.CLC.B.DISR = 1;                       \
 *     IfxScuWdt_setCpuEndinit(passwd);                   \
 * }
 */

 

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Thank you for the response.

Could you please let me know which code example  in the github has the above code snippet you sent please, because I have used the same functions from code examples like below 

Anusha_k_rao_0-1664866876581.png

Even then I'm not able to write or read the CPU.SEGEN.

If the endinit protection is not removed or if the timer is timed out, I should not be able to write to CPU.SEGEN but I'm not able to read it either, I'm not sure why is it.  I don't think any registers have to be enabled even for reading the CPU.SEGEN, is it? Or please do enlighten me if I have missed any here.

Anusha_k_rao_1-1664867130485.png

When I execute above reading of CPU.SEGEN it gets into exception. [MODULE_CPU0 = 0xF8800000H]

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Di_W
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        /* Set PSW.IO to 2 (supervisor mode). This is needed for certain operations
         * performed below. */
        __mtcr(PSW, (int) (((unsigned int) __mfcr(PSW) & 0xfffff3ffU) | 0x800U));

Please try to use supervisor mode

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