In TC36x or TC38x, how does simultaneous access from multiple cores to same RAM region is handled by MCU?

[Ptar]

If DLMU0 RAM can be accessed by both CPU0 and CPU1, then how does the simultaneous write is handled?

If we are using DLMU0 RAM to share the global variables across core, how does the write from different cores is handled?

[Prudhvi_E · Accepted solution]

Hello,

If there is a request from more than one Master then the Arbitration happens based on the priority (MCI number) using a round-robin method the access is granted.  Please refer to "4.3 Functional Description" section in the "4 On-Chip System Connectivity" chapter in detail for more information. I would suggest to go through the chapter and please let us know if you have a specific question.

Regards,

Prudhvi.

[Ptar]

OK. That means based on the priority settings in the SCIx Arbiter Priority Register, the write or read request from the CPU0 and CPU1 at same time will win the arbitration.

Before completing the write/read operation, whether next request will be accepted?