ILLD SpiSlaver

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jica-zhang
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Hello, may I ask some problems encountered when debugging the ILLD SPIslaver code?

1: Whether the ILLD code supports variable length data (such as accepting 8 bytes /10 bytes)

2. Why does IfxQspi_SpiSlave_write () add 1 to TXFIFOLEVEL after writing 3 bytes of data to txfifo, Then the call to IfxQspi_SpiSlave_write () in the interrupt writes 2 bytes of TXFIFOLEVEL bytes instead of 3. How many bytes of data can each TXFIFOLEVEL write?

3: How to clear TXFIFO after SPI initialization? qspi-> globalcon.b.res =0X11 causes SPI to send data with a fixed error value

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Di_W
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Please refer to the code for master and slave SPI settings:

void initQSPI(void)
{
    /* Firstly initialize the Slave */
    initQSPI3Slave();
    initQSPI3SlaveBuffers();

    /* Secondly initialize the Master */
    initQSPI2Master();
    initQSPI2MasterChannel();
    initQSPI2MasterBuffers();
}

 

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这是一个初始化代码,你没有回答我的问题

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This is an initialization code, you didn't answer my question

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Di_W
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For TXFIFO, there are Single Move Mode/Batch Move Mode/ Combined Mode. It's suggested start from Single Move Mode. When in Single Move Mode, you can write TXFIFO when interrupt which tell you there is an empty position.

For TXFIFOLEVEL, there is 0,1,2,3,4 settings. You can read to know how many left to send.Reading the TXFIFO filling level bit field returns a value which can be used to calculate how many writes can be performed by a CPU without causing an overflow .

TXFIFOINT only be effective in BATCH MODE and COMBINED MODE.

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May I ask why after the initialization of spi is completed and normal operation, directly calling qspi-> globalcon.b.es =0X01 after clearing rxfifo and txfifo, all the data sent by spi will be wrong? Or what do I need to empty txfifo after spi works?

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Di_W
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typedef struct _Ifx_QSPI_GLOBALCON_Bits
{
    Ifx_UReg_32Bit TQ:8;              /**< \brief [7:0] Global Time Quantum Length - TQ (rw) */
    Ifx_UReg_32Bit reserved_8:1;      /**< \brief [8:8] \internal Reserved */
    Ifx_UReg_32Bit SI:1;              /**< \brief [9:9] Status Injection - SI (rw) */
    Ifx_UReg_32Bit EXPECT:4;          /**< \brief [13:10] Time-Out Value for the Expect Phase - EXPECT (rw) */
    Ifx_UReg_32Bit LB:1;              /**< \brief [14:14] Loop-Back Control - LB (rw) */
    Ifx_UReg_32Bit DEL0:1;            /**< \brief [15:15] Delayed Mode for SLSO0 - DEL0 (rw) */
    Ifx_UReg_32Bit STROBE:5;          /**< \brief [20:16] Strobe Delay for SLSO0 in Delayed Mode - STROBE (rw) */
    Ifx_UReg_32Bit SRF:1;             /**< \brief [21:21] Stop on RxFIFO Full - SRF (rw) */
    Ifx_UReg_32Bit STIP:1;            /**< \brief [22:22] Slave Transmit Idle State Polarity - STIP (rw) */
    Ifx_UReg_32Bit reserved_23:1;     /**< \brief [23:23] \internal Reserved */
    Ifx_UReg_32Bit EN:1;              /**< \brief [24:24] Enable Bit - EN (rwh) */
    Ifx_UReg_32Bit MS:2;              /**< \brief [26:25] Master Slave Mode - MS (rw) */
    Ifx_UReg_32Bit AREN:1;            /**< \brief [27:27] Automatic Reset Enable - AREN (rw) */
    Ifx_UReg_32Bit reserved_28:1;     /**< \brief [28:28] \internal Reserved */
    Ifx_UReg_32Bit CLKSEL:1;          /**< \brief [29:29] Clock Select - CLKSEL (rw) */
    Ifx_UReg_32Bit RESETS:2;          /**< \brief [31:30] Bits for resetting sub-modules per software - RESETS (w) */
} Ifx_QSPI_GLOBALCON_Bits;

Could you please confirm ES bitfield?

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Is it ES or EN?

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Di_W
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Please refer to above struct, there is no ES, so I am confusing.

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  • What does this ES bit do?

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Di_W
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No idea, could you please post your struct of globalcon.b?

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typedef struct _Ifx_QSPI_GLOBALCON_Bits
{
Ifx_UReg_32Bit TQ:8; /**< \brief [7:0] Global Time Quantum Length - TQ (rw) */
Ifx_UReg_32Bit reserved_8:1; /**< \brief [8:8] \internal Reserved */
Ifx_UReg_32Bit SI:1; /**< \brief [9:9] Status Injection - SI (rw) */
Ifx_UReg_32Bit EXPECT:4; /**< \brief [13:10] Time-Out Value for the Expect Phase - EXPECT (rw) */
Ifx_UReg_32Bit LB:1; /**< \brief [14:14] Loop-Back Control - LB (rw) */
Ifx_UReg_32Bit DEL0:1; /**< \brief [15:15] Delayed Mode for SLSO0 - DEL0 (rw) */
Ifx_UReg_32Bit STROBE:5; /**< \brief [20:16] Strobe Delay for SLSO0 in Delayed Mode - STROBE (rw) */
Ifx_UReg_32Bit SRF:1; /**< \brief [21:21] Stop on RxFIFO Full - SRF (rw) */
Ifx_UReg_32Bit STIP:1; /**< \brief [22:22] Slave Transmit Idle State Polarity - STIP (rw) */
Ifx_UReg_32Bit reserved_23:1; /**< \brief [23:23] \internal Reserved */
Ifx_UReg_32Bit EN:1; /**< \brief [24:24] Enable Bit - EN (rwh) */
Ifx_UReg_32Bit MS:2; /**< \brief [26:25] Master Slave Mode - MS (rw) */
Ifx_UReg_32Bit AREN:1; /**< \brief [27:27] Automatic Reset Enable - AREN (rw) */
Ifx_UReg_32Bit reserved_28:1; /**< \brief [28:28] \internal Reserved */
Ifx_UReg_32Bit CLKSEL:1; /**< \brief [29:29] Clock Select - CLKSEL (rw) */
Ifx_UReg_32Bit RESETS:2; /**< \brief [31:30] Bits for resetting sub-modules per software - RESETS (w) */
} Ifx_QSPI_GLOBALCON_Bits;

  • Mine doesn't have ES either

 

 

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Di_W
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qspi-> globalcon.b.es =0X01 

So I am not aware of this bit setting at all.

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qspi-> globalcon.b.RESETS=0x01
  • The wrong number is this one

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I would like to ask whether SPI Slaver can accept data of indefinite length in one frame? For example, a frame of data has 8 bytes and 10 bytes and 12 words. Can you do that?

 

  • As an aside, are the moderators Chinese?

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Di_W
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In the Long Data Mode, QSPI can transmit up to 32 byte in one frame. Please refer to 37.3.5.1.2 Long Data Mode in user manual. Short Data Mode can send 2-32bits in one frame.

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May I ask why after the initialization of spi is completed and normal operation, directly calling qspi-> globalcon.b.rest =0X01 after clearing rxfifo and txfifo, all the data sent by spi will be wrong? Or what do I need to empty txfifo after spi works?

  • May I ask the next moderator, how to clear fifo

 

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Di_W
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Do you mean globalcon.b.RESETS or globalcon.b.rest? If RESETS, that means the subset of module is reset, and if your SPI Master still send SLK signal, the output data will not be correct. Could you please try to reconfigure the SPI after globalcon.b.RESETS = 0x01.

Please refer to 37.3.7 Reset Behavior.

 

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