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cross mob
User16347
Level 1
Level 1
Like to implement an I2C Master-Receiver.

I managed to implement it in 2 steps:
- send START / Chip-Address(Wr) / 1 data-byte / STOP
- here an ISR gets triggered, that starts the 2. step:
- START / Chip-Address(Rd) / data (1...10) / STOP

What I want to achieve is:
- send START / Chip-Address(Wr) / 1 data-byte / REPEATED_START / Chip-Address(Rd) / data (1...10) / STOP

Is it possible to have this sequence generated by filling the FIFO at the beginning, without further CPU/DMA-actions ?

Peter
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2 Replies
MoD
Employee
Employee
50 likes received 500 replies posted 100 solutions authored
This can't be achieve by filling the FIFO 1 time, this must be done in 2 sequences (by CPU or DMA): first START / Chip-Address(Wr) / 1 data-byte second: REPEATED_START / Chip-Address(Rd) / data (1...10)
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User16347
Level 1
Level 1
Thank you, MoD, this may save me a lot of time !

Peter
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