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TC3XXのユーザーマニュアルには、大きな範囲(0x8000 - 0xBFFC)はFIFO用と記載されています。

しかし、 を書くときは、TXD(0x8000) のみを使用し、範囲 (0x8004 - 0xBFFC) は予約されています。

では、I2C書込みの範囲(0x8004 - 0xBFFC)をどのように使用できますか? 書き込みデータを範囲(0x8000 - 0xBFFC)に直接コピーできますか?または、他のレジスタを構成する必要がありますか?

xiaotiancai_0-1700198968996.png

xiaotiancai_1-1700199003963.png

 

xiaotiancai_2-1700199029517.png

 

 

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/How-to-use-I2C-FIFO-register-address-range-0x8000-0xBFFC/td-p/642703

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Translation_Bot
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0x8000をTXDとして使用し、他のアドレスは無視してください。 以下のI2Cオブジェクトの構造を参照してください。

 

/** \brief I2C object */
typedef volatile struct _Ifx_I2C
{
       Ifx_I2C_CLC1                        CLC1;                   /**< \brief 0, Clock Control 1 Register*/
       Ifx_UReg_8Bit                       reserved_4[4];          /**< \brief 4, \internal Reserved */
       Ifx_I2C_ID                          ID;                     /**< \brief 8, Module Identification Register*/
       Ifx_UReg_8Bit                       reserved_C[4];          /**< \brief C, \internal Reserved */
       Ifx_I2C_RUNCTRL                     RUNCTRL;                /**< \brief 10, RUN Control Register*/
       Ifx_I2C_ENDDCTRL                    ENDDCTRL;               /**< \brief 14, End Data Control Register*/
       Ifx_I2C_FDIVCFG                     FDIVCFG;                /**< \brief 18, Fractional Divider Configuration Register*/
       Ifx_I2C_FDIVHIGHCFG                 FDIVHIGHCFG;            /**< \brief 1C, Fractional Divider High-speed Mode Configuration Register*/
       Ifx_I2C_ADDRCFG                     ADDRCFG;                /**< \brief 20, Address Configuration Register*/
       Ifx_I2C_BUSSTAT                     BUSSTAT;                /**< \brief 24, Bus Status Register*/
       Ifx_I2C_FIFOCFG                     FIFOCFG;                /**< \brief 28, FIFO Configuration Register*/
       Ifx_I2C_MRPSCTRL                    MRPSCTRL;               /**< \brief 2C, Maximum Received Packet Size Control Register*/
       Ifx_I2C_RPSSTAT                     RPSSTAT;                /**< \brief 30, Received Packet Size Status Register*/
       Ifx_I2C_TPSCTRL                     TPSCTRL;                /**< \brief 34, Transmit Packet Size Control Register*/
       Ifx_I2C_FFSSTAT                     FFSSTAT;                /**< \brief 38, Filled FIFO Stages Status Register*/
       Ifx_UReg_8Bit                       reserved_3C[4];         /**< \brief 3C, \internal Reserved */
       Ifx_I2C_TIMCFG                      TIMCFG;                 /**< \brief 40, Timing Configuration Register*/
       Ifx_UReg_8Bit                       reserved_44[28];        /**< \brief 44, \internal Reserved */
       Ifx_I2C_ERRIRQSM                    ERRIRQSM;               /**< \brief 60, Error Interrupt Request Source Mask Register*/
       Ifx_I2C_ERRIRQSS                    ERRIRQSS;               /**< \brief 64, Error Interrupt Request Source Status Register*/
       Ifx_I2C_ERRIRQSC                    ERRIRQSC;               /**< \brief 68, Error Interrupt Request Source Clear Register*/
       Ifx_UReg_8Bit                       reserved_6C[4];         /**< \brief 6C, \internal Reserved */
       Ifx_I2C_PIRQSM                      PIRQSM;                 /**< \brief 70, Protocol Interrupt Request Source Mask Register*/
       Ifx_I2C_PIRQSS                      PIRQSS;                 /**< \brief 74, Protocol Interrupt Request Source Status Register*/
       Ifx_I2C_PIRQSC                      PIRQSC;                 /**< \brief 78, Protocol Interrupt Request Source Clear Register*/
       Ifx_UReg_8Bit                       reserved_7C[4];         /**< \brief 7C, \internal Reserved */
       Ifx_I2C_RIS                         RIS;                    /**< \brief 80, Raw Interrupt Status Register*/
       Ifx_I2C_IMSC                        IMSC;                   /**< \brief 84, Interrupt Mask Control Register*/
       Ifx_I2C_MIS                         MIS;                    /**< \brief 88, Masked Interrupt Status Register*/
       Ifx_I2C_ICR                         ICR;                    /**< \brief 8C, Interrupt Clear Register*/
       Ifx_I2C_ISR                         ISR;                    /**< \brief 90, Interrupt Set Register*/
       Ifx_UReg_8Bit                       reserved_94[32620];     /**< \brief 94, \internal Reserved */
       Ifx_I2C_TXD                         TXD;                    /**< \brief 8000, Transmission Data Register*/
       Ifx_UReg_8Bit                       reserved_8004[16380];    /**< \brief 8004, \internal Reserved */
       Ifx_I2C_RXD                         RXD;                    /**< \brief C000, Reception Data Register*/
       Ifx_UReg_8Bit                       reserved_C004[16380];    /**< \brief C004, \internal Reserved */
       Ifx_I2C_CLC                         CLC;                    /**< \brief 10000, Clock Control Register*/
       Ifx_I2C_MODID                       MODID;                  /**< \brief 10004, Module Identification Register*/
       Ifx_I2C_GPCTL                       GPCTL;                  /**< \brief 10008, General Purpose Control Register*/
       Ifx_I2C_ACCEN0                      ACCEN0;                 /**< \brief 1000C, Access Enable Register 0*/
       Ifx_I2C_ACCEN1                      ACCEN1;                 /**< \brief 10010, Access Enable Register 1*/
       Ifx_I2C_KRST0                       KRST0;                  /**< \brief 10014, Kernel Reset Register 0*/
       Ifx_I2C_KRST1                       KRST1;                  /**< \brief 10018, Kernel Reset Register 1*/
       Ifx_I2C_KRSTCLR                     KRSTCLR;                /**< \brief 1001C, Kernel Reset Status Clear Register*/
       Ifx_UReg_8Bit                       reserved_10020[222];    /**< \brief 10020, \internal Reserved */
} Ifx_I2C;

 

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/How-to-use-I2C-FIFO-register-address-range-0x8000-0xBFFC/m-p/643201

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0x8000をTXDとして使用し、他のアドレスは無視してください。 以下のI2Cオブジェクトの構造を参照してください。

 

/** \brief I2C object */
typedef volatile struct _Ifx_I2C
{
       Ifx_I2C_CLC1                        CLC1;                   /**< \brief 0, Clock Control 1 Register*/
       Ifx_UReg_8Bit                       reserved_4[4];          /**< \brief 4, \internal Reserved */
       Ifx_I2C_ID                          ID;                     /**< \brief 8, Module Identification Register*/
       Ifx_UReg_8Bit                       reserved_C[4];          /**< \brief C, \internal Reserved */
       Ifx_I2C_RUNCTRL                     RUNCTRL;                /**< \brief 10, RUN Control Register*/
       Ifx_I2C_ENDDCTRL                    ENDDCTRL;               /**< \brief 14, End Data Control Register*/
       Ifx_I2C_FDIVCFG                     FDIVCFG;                /**< \brief 18, Fractional Divider Configuration Register*/
       Ifx_I2C_FDIVHIGHCFG                 FDIVHIGHCFG;            /**< \brief 1C, Fractional Divider High-speed Mode Configuration Register*/
       Ifx_I2C_ADDRCFG                     ADDRCFG;                /**< \brief 20, Address Configuration Register*/
       Ifx_I2C_BUSSTAT                     BUSSTAT;                /**< \brief 24, Bus Status Register*/
       Ifx_I2C_FIFOCFG                     FIFOCFG;                /**< \brief 28, FIFO Configuration Register*/
       Ifx_I2C_MRPSCTRL                    MRPSCTRL;               /**< \brief 2C, Maximum Received Packet Size Control Register*/
       Ifx_I2C_RPSSTAT                     RPSSTAT;                /**< \brief 30, Received Packet Size Status Register*/
       Ifx_I2C_TPSCTRL                     TPSCTRL;                /**< \brief 34, Transmit Packet Size Control Register*/
       Ifx_I2C_FFSSTAT                     FFSSTAT;                /**< \brief 38, Filled FIFO Stages Status Register*/
       Ifx_UReg_8Bit                       reserved_3C[4];         /**< \brief 3C, \internal Reserved */
       Ifx_I2C_TIMCFG                      TIMCFG;                 /**< \brief 40, Timing Configuration Register*/
       Ifx_UReg_8Bit                       reserved_44[28];        /**< \brief 44, \internal Reserved */
       Ifx_I2C_ERRIRQSM                    ERRIRQSM;               /**< \brief 60, Error Interrupt Request Source Mask Register*/
       Ifx_I2C_ERRIRQSS                    ERRIRQSS;               /**< \brief 64, Error Interrupt Request Source Status Register*/
       Ifx_I2C_ERRIRQSC                    ERRIRQSC;               /**< \brief 68, Error Interrupt Request Source Clear Register*/
       Ifx_UReg_8Bit                       reserved_6C[4];         /**< \brief 6C, \internal Reserved */
       Ifx_I2C_PIRQSM                      PIRQSM;                 /**< \brief 70, Protocol Interrupt Request Source Mask Register*/
       Ifx_I2C_PIRQSS                      PIRQSS;                 /**< \brief 74, Protocol Interrupt Request Source Status Register*/
       Ifx_I2C_PIRQSC                      PIRQSC;                 /**< \brief 78, Protocol Interrupt Request Source Clear Register*/
       Ifx_UReg_8Bit                       reserved_7C[4];         /**< \brief 7C, \internal Reserved */
       Ifx_I2C_RIS                         RIS;                    /**< \brief 80, Raw Interrupt Status Register*/
       Ifx_I2C_IMSC                        IMSC;                   /**< \brief 84, Interrupt Mask Control Register*/
       Ifx_I2C_MIS                         MIS;                    /**< \brief 88, Masked Interrupt Status Register*/
       Ifx_I2C_ICR                         ICR;                    /**< \brief 8C, Interrupt Clear Register*/
       Ifx_I2C_ISR                         ISR;                    /**< \brief 90, Interrupt Set Register*/
       Ifx_UReg_8Bit                       reserved_94[32620];     /**< \brief 94, \internal Reserved */
       Ifx_I2C_TXD                         TXD;                    /**< \brief 8000, Transmission Data Register*/
       Ifx_UReg_8Bit                       reserved_8004[16380];    /**< \brief 8004, \internal Reserved */
       Ifx_I2C_RXD                         RXD;                    /**< \brief C000, Reception Data Register*/
       Ifx_UReg_8Bit                       reserved_C004[16380];    /**< \brief C004, \internal Reserved */
       Ifx_I2C_CLC                         CLC;                    /**< \brief 10000, Clock Control Register*/
       Ifx_I2C_MODID                       MODID;                  /**< \brief 10004, Module Identification Register*/
       Ifx_I2C_GPCTL                       GPCTL;                  /**< \brief 10008, General Purpose Control Register*/
       Ifx_I2C_ACCEN0                      ACCEN0;                 /**< \brief 1000C, Access Enable Register 0*/
       Ifx_I2C_ACCEN1                      ACCEN1;                 /**< \brief 10010, Access Enable Register 1*/
       Ifx_I2C_KRST0                       KRST0;                  /**< \brief 10014, Kernel Reset Register 0*/
       Ifx_I2C_KRST1                       KRST1;                  /**< \brief 10018, Kernel Reset Register 1*/
       Ifx_I2C_KRSTCLR                     KRSTCLR;                /**< \brief 1001C, Kernel Reset Status Clear Register*/
       Ifx_UReg_8Bit                       reserved_10020[222];    /**< \brief 10020, \internal Reserved */
} Ifx_I2C;

 

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/How-to-use-I2C-FIFO-register-address-range-0x8000-0xBFFC/m-p/643201

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