AURIX™ Forum Discussions

[DownyK]

Hi everyone,

After MCU performs Lbist at App SW level, it jumps to the start address after SW reset (system reset).

After that, before going to the actual application address, several registers are checked, one of which is CPU0 KRST0 RSTSTAT. But when I check this register, the trap is occurring.

Have any of you ever experienced this situation?

[Nambi]

Hi,

1. "when I check this register,." Are you just reading this register or also writing to this register?

2. Can you comment the access to this register in your code and confirm that the system is working fine?

Best Regards.

[DownyK]

Hi Nambi

I tried to read the CPU0 KRST0 register and trap 2 occurs.

Yes, if I comment this code to access this register,  the system works fine.

CPU0 KRST0 : 0xF880D000

[MoD]

You get a Trap Class 4 -> DSE - Data Access Synchronous Error (TIN 2)

Set a breakpoint on address 0xA000C5BE and analyze the instruction and the content of used register with this instruction. I expect that there is a wrong value use which result to a read access to an invalid address.

[DownyK]

Hi MoD

Thank you for your reply.

Our team noticed something odd in the compiled code.

A trap occurs when reading CPU0_KRST0 in byte units [ld.bu] and no trap occurs when reading in word units [ld.w].

Does the register have to be read in word units only?

If you know anything about this, please share.

[MoD · Accepted solution]

The register can't be read with ld.b or ld.h. It must be accessed always with 32 bit width:

[DownyK]

oh thanks, I didn't check it 

[Prudhvi]

Hello DownyK,

Please find the Access modes for Read/Write below:

As mentioned here, the Register is to be read/written in 32 bits.

Regards,

Prudhvi.