How  to use TC397 MDIO, MDC to configure external ethernet PHY?

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
lock attach
Attachments are accessible only for community members.
E-John
Level 3
Level 3
10 replies posted First like given 25 sign-ins

Dear all,

How  to use MDIO, MDC to configure external ethernet PHY?

  • RTL8211FI-CG Eth Phy is used by TriBoard  (Fig.1)
  • refer to Infineon Triboard codebase “TriBoard_TC39XB_V1.1.0” IfxGeth_Phy_Rtl8211f.c
    1.  It seems to set TC397 MAC registers only either in MDIO_Write or MDIO_Read API(see code snippet)?
    2.  Should it be set some data in buffer then send out to external ethernet PHY for MDIO, MDC? Do I missing something?
// MDIO write to SOC’s Ethernet register banks
void IfxGeth_Eth_Phy_Rtl8211f_write_mdio_reg(uint32 layeraddr, uint32 regaddr, uint32 data)
{
    // put data
   GETH_MAC_MDIO_DATA.U = data;

    // 5bit Physical Layer Adddress, 5bit GMII Regnr, 4bit csrclock divider, Write, Busy
    GETH_MAC_MDIO_ADDRESS.U = (layeraddr << 21) | (regaddr << 16) | (0 << 😎 |  (1 << 2) | (1 << 0);

    IFXGETH_PHY_RTL8211F_WAIT_MDIO_READY();
}
//MDIO read from SOC’s Ethernet register banks
void IfxGeth_Eth_Phy_Rtl8211f_read_mdio_reg(uint32 layeraddr, uint32 regaddr, uint32 *pdata)
{
    // 5bit Physical Layer Adddress, 5bit GMII Regnr, 4bit csrclock divider, Read, Busy
   GETH_MAC_MDIO_ADDRESS.U = (layeraddr << 21) | (regaddr << 16) | (0 << 😎 | (3 << 2) | (1 << 0);

   IFXGETH_PHY_RTL8211F_WAIT_MDIO_READY();

    // get data
   *pdata = GETH_MAC_MDIO_DATA.U;
}
0 Likes
2 Replies
Prudhvi_E
Moderator
Moderator
Moderator
250 replies posted 100 solutions authored 25 likes received

Hello,

MDIO is a register based interface were you read and write from them. There is no buffer needed.

Regards,

Prudhvi.

0 Likes

Hi Prudhvi,

From your explanation, reference code and documentation.

It seems that what we need to do is

1. Set values to these two registers, GETH_MAC_MDIO_DATA and GETH_MAC_MDIO_ADDRESS and follow the write/read sequences on Fig 698 SMA Write Operation Flow. (Fig.1 below)

2. The "DWC_ether_qos IP provided by Synosys" will help us write/read the data to/from the external ethernet PHY registers defined by IEEE 802.3 Clause 22, Clause 45 write/read timing. (Fig.2 below), refer to https://en.wikipedia.org/wiki/Management_Data_Input/Output

 

01-TC397_SMA_reg.png

Fig.1

02-c22_c45_timing.png

Fig.2

 

 

0 Likes