How to test SRI Transaction error

[Marwaaboelamay]

AURIXtc33x 

we found this but we need more clarification for example :

we need to test the MC1 (SFI F2S ) and MC2 (CPU0) , so how we can inject non correctable error for them ? 

or there is another way to inject the fault for them to be able to test their interrupt .

[LaneYE · Accepted solution]

Hi, Marwaaboelamay

As user manual said, if the data phase(Read/write) is invalidated, the MCI or SCI will send an invalid transaction ID, so we can inject a non-correctable error into RAM , then readback the error RAM.

HOW TO INJECT THE ERROR

You can modify the ECCMAP bits to introduce multi bits by programming a word with wrong ecc.

ECCMAP = 01b, Test mode

[Marwaaboelamay]

as you see in the screenshot , i cannot access any of MTU or SRAM registers during the SW running because it goes to SW reset once open any of these registers so how can i  odify the ECCMAP bits?

[LaneYE]

Hi, Marwaaboelamay

I don't know why you can't watch these registers.Is it same effect(reset) when you watch other registers?

Additional, the MCi_ECCS register is protected by End-Init mechanism, so you can't modify directly in debug.

[Marwaaboelamay]

no i can watch other registers except MTU and SRAM registers,

so how can i modify the MCi_ECCS? 

[LaneYE]

Hi, Marwaaboelamay

no i can watch other registers except MTU and SRAM registers,

>>I can't explain it, maybe you could contact your FAE for supporting;

so how can i modify the MCi_ECCS?

>>You could reference "The Endinit Functions", before you modify the registers protected by Endinit, you should unlock first and lock it after you modified. It's a HW safety mechanism to avoid unintended modify.

[Aiswarya_A]

Hello, 

Is this issue resolved?

These registers should be readable, you could confirm if the MTU and SRAM modules are enabled.
You could also refer to this code example.

Kind Regards,
Aiswarya.